drivers/intel/gma: Drop unused INTEL_DP
Change-Id: I786848cd48c6fcfecf9b72c60623cadcfcbb7db7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Nico Huber
parent
0df9a01009
commit
746aa054e2
@ -14,12 +14,6 @@
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## GNU General Public License for more details.
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##
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config INTEL_DP
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bool
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default n
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help
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helper functions for intel display port operations
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config INTEL_DDI
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bool
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default n
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@ -13,7 +13,6 @@
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## GNU General Public License for more details.
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##
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ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c display.c
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ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c
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ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c
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ifeq ($(CONFIG_VGA_ROM_RUN),y)
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@ -1,119 +0,0 @@
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/*
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* Copyright 2013 Google Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Keith Packard <keithp@keithp.com>
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*
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*/
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/* This code was created by the coccinnelle filters in the i915tool,
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* with some final hand filtering.
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*/
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#include <console/console.h>
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#include <stdint.h>
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#include <delay.h>
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#include <drivers/intel/gma/i915.h>
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#include <string.h>
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void compute_display_params(struct intel_dp *dp)
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{
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struct edid *edid = &(dp->edid);
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struct edid_mode *mode = &edid->mode;
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/* step 1: get the constants in the dp struct set up. */
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dp->lane_count = dp->dpcd[DP_MAX_LANE_COUNT]&DP_LANE_COUNT_MASK;
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dp->link_bw = dp->dpcd[DP_MAX_LINK_RATE];
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dp->clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
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dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
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/* step 2. Do some computation of other stuff. */
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dp->bytes_per_pixel = dp->pipe_bits_per_pixel/8;
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dp->stride = edid->bytes_per_line;
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dp->htotal = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16);
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dp->hblank = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16);
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dp->hsync = (mode->ha + mode->hso - 1) |
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((mode->ha + mode->hso + mode->hspw - 1) << 16);
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dp->vtotal = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16);
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dp->vblank = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16);
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dp->vsync = (mode->va + mode->vso - 1) |
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((mode->va + mode->vso + mode->vspw - 1) << 16);
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/* PIPEASRC is wid-1 x ht-1 */
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dp->pipesrc = (mode->ha-1)<<16 | (mode->va-1);
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dp->pfa_pos = 0;
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dp->pfa_ctl = PF_ENABLE | PF_FILTER_MED_3x3;
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/* IVB hack */
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if (dp->gen == 6)
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dp->pfa_ctl |= PF_PIPE_SEL_IVB(dp->pipe);
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dp->pfa_sz = (mode->ha << 16) | (mode->va);
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/* step 3. Call the linux code we pulled in. */
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dp->flags = intel_ddi_calc_transcoder_flags(edid->panel_bits_per_pixel,
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dp->port,
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dp->pipe,
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dp->type,
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dp->lane_count,
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dp->pfa_sz,
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mode->phsync == '+'?1:0,
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mode->pvsync == '+'?1:0);
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dp->transcoder = intel_ddi_get_transcoder(dp->port,
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dp->pipe);
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intel_dp_compute_m_n(edid->panel_bits_per_pixel,
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dp->lane_count,
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dp->edid.mode.pixel_clock,
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dp->edid.link_clock,
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&dp->m_n);
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printk(BIOS_SPEW, "dp->lane_count = 0x%08x\n",dp->lane_count);
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printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
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printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
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printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
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printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
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printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
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printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
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printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
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printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
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printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
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printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
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printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
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printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
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printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
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printk(BIOS_SPEW, "0x6f030 = 0x%08x\n",
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TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
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printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
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printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
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printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
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}
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@ -1,119 +0,0 @@
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/*
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* Copyright 2013 Google Inc.
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* Copyright © 2009 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#include <console/console.h>
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#include <stdint.h>
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#include <delay.h>
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#include <drivers/intel/gma/i915.h>
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#include <string.h>
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#include <edid.h>
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/* reduced a lot for coreboot. */
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/**
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* DOC: dp helpers
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*
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* These functions contain some common logic and helpers at various
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* abstraction levels to deal with Display Port sink devices and
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* related things like DP aux channel transfers, EDID reading over DP
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* aux channels, decoding certain DPCD blocks, ...
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*/
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/* Helpers for DP link training */
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static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
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{
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printk(BIOS_SPEW, "%s: %d, %d, %d\n", __func__,
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r, r - DP_LANE0_1_STATUS,
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link_status[r - DP_LANE0_1_STATUS]);
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return link_status[r - DP_LANE0_1_STATUS];
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}
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static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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int s = (lane & 1) * 4;
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u8 l = dp_link_status(link_status, i);
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return (l >> s) & 0xf;
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}
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int drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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u8 lane_align;
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u8 lane_status;
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int lane;
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lane_align = dp_link_status(link_status,
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DP_LANE_ALIGN_STATUS_UPDATED);
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if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
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return 0;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
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return 0;
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}
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return 1;
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}
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int drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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int lane;
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u8 lane_status;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_LANE_CR_DONE) == 0)
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return 0;
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}
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return 1;
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}
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u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
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DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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printk(BIOS_SPEW, "%s: i %d s %d l %d return %d\n",
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__func__, i, s, l,
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((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT);
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return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
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}
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u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
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int s = ((lane & 1) ?
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DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
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DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
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u8 l = dp_link_status(link_status, i);
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return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
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}
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@ -81,201 +81,7 @@ enum {
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unsigned long io_i915_read32(unsigned long addr);
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void io_i915_write32(unsigned long val, unsigned long addr);
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/*
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* To communicate to and control the extracted-from-kernel code,
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* we need this struct. It has a counterpart in the ARM code, so
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* there is a precedent.
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*/
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#define DP_RECEIVER_CAP_SIZE 0xf
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#define DP_LINK_STATUS_SIZE 6
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#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
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#define DP_LINK_CONFIGURATION_SIZE 9
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struct intel_dp_m_n {
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uint32_t tu;
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uint32_t gmch_m;
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uint32_t gmch_n;
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uint32_t link_m;
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uint32_t link_n;
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};
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struct intel_dp {
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int gen; // 6 for link, 7 for wtm2
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int has_pch_split; // 1 for link and wtm2
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int has_pch_cpt; // 1 for everything we know about.
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int is_haswell;
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/* output register offset in MMIO space. Usually DP_A */
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u32 output_reg;
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/* The initial value of the DP register.
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* Mainboards can set this to a non-zero
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* value in the case that there are undetectable
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* but essential parameters.
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*/
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u32 DP;
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uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
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u32 color_range;
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/* these paramaters are determined after reading the DPCD */
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int dpms_mode;
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uint8_t link_bw;
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uint8_t lane_count;
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/* This data is read from the panel via the AUX channel.*/
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uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
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int type;
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int edp;
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int is_pch_edp;
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/* state related to training. */
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uint8_t train_set[4];
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/* Determined from EDID or coreboot hard-sets. */
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int panel_power_up_delay;
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int panel_power_down_delay;
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int panel_power_cycle_delay;
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int backlight_on_delay;
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int backlight_off_delay;
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int want_panel_vdd;
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u32 clock;
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int port;
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int pipe;
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int plane;
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int pipe_bits_per_pixel;
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/* i2c on aux is ... interesting.
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* Before you do an i2c cycle, you need to set the address.
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* This requires we remember it from one moment to the next.
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* Remember it here.
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*/
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u16 address;
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/* timing parameters for aux channel IO. They used to compute these on
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* each and every entry to the functions, which is kind of stupid, and it had
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* errors anyway.
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* note: you can get these from watching YABEL output. E.g.:
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* you see an outb of 0x802300e1 to 64010. the 3 is the precharge
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* and the e1 is the clock divider.
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*/
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u32 aux_clock_divider;
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u32 precharge;
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/* EDID, raw and processed */
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u8 rawedid[256];
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int edidlen;
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struct edid edid;
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/* computed values needed for "i915" registers */
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int bytes_per_pixel;
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u32 htotal;
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u32 hblank;
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u32 hsync;
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u32 vtotal;
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u32 vblank;
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u32 vsync;
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u32 pfa_sz;
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u32 pfa_pos;
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u32 pfa_ctl;
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u32 pipesrc;
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u32 stride;
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struct intel_dp_m_n m_n;
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u32 flags;
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u32 transcoder;
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/* parameters computed by the early startup, to be used
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* in the GMA code.
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*/
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u8 *graphics;
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/* physical address, not to be used directly. */
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u64 physbase;
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};
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/* we may yet need these. */
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void intel_dp_mode_set(struct intel_dp *intel_dp);
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void intel_dp_start_link_train(struct intel_dp *intel_dp);
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int intel_dp_i2c_init(struct intel_dp *intel_dp);
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int intel_dp_i2c_aux_ch(struct intel_dp *intel_dp,
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int mode, uint8_t write_byte, uint8_t *read_byte);
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int intel_dp_get_dpcd(struct intel_dp *intel_dp);
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struct edid *intel_dp_get_edid(struct intel_dp *intel_dp);
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void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
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void ironlake_edp_pll_on(void);
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void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
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void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, int sync);
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int intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread);
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void ironlake_edp_panel_on(struct intel_dp *intel_dp);
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void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
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/* needed only on haswell. */
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void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port);
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int intel_dp_aux_ch(struct intel_dp *intel_dp,
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uint8_t *send, int send_bytes,
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uint8_t *recv, int recv_size);
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void unpack_aux(u32 src, uint8_t *dst, int dst_bytes);
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int intel_channel_eq_ok(struct intel_dp *intel_dp,
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uint8_t link_status[DP_LINK_STATUS_SIZE]);
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void ironlake_edp_panel_off(struct intel_dp *intel_dp);
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void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
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/* drm_dp_helper.c */
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int drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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int drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane);
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u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane);
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void intel_dp_wait_reg(unsigned long addr,
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unsigned long val);
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void intel_dp_wait_panel_power_control(unsigned long val);
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void intel_dp_compute_m_n(unsigned int bits_per_pixel,
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unsigned int nlanes,
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unsigned int pixel_clock,
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unsigned int link_clock,
|
||||
struct intel_dp_m_n *m_n);
|
||||
|
||||
u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp,
|
||||
enum port port,
|
||||
enum pipe pipe,
|
||||
int type,
|
||||
int lane_count,
|
||||
int pf_sz,
|
||||
u8 phsync,
|
||||
u8 pvsync);
|
||||
|
||||
enum transcoder intel_ddi_get_transcoder(enum port port,
|
||||
enum pipe pipe);
|
||||
|
||||
void intel_dp_set_m_n_regs(struct intel_dp *intel_dp);
|
||||
int intel_dp_bw_code_to_link_rate(u8 link_bw);
|
||||
void intel_dp_set_resolution(struct intel_dp *intel_dp);
|
||||
|
||||
int intel_dp_i2c_write(struct intel_dp *intel_dp,
|
||||
u8 val);
|
||||
|
||||
int intel_dp_i2c_read(struct intel_dp *intel_dp,
|
||||
u8 *val);
|
||||
|
||||
int intel_dp_set_bw(struct intel_dp *intel_dp);
|
||||
int intel_dp_set_lane_count(struct intel_dp *intel_dp);
|
||||
int intel_dp_set_training_lane0(struct intel_dp *intel_dp,
|
||||
u8 val);
|
||||
int intel_dp_set_training_pattern(struct intel_dp *intel_dp,
|
||||
u8 pat);
|
||||
|
||||
int intel_dp_get_link_status(struct intel_dp *intel_dp,
|
||||
uint8_t link_status[DP_LINK_STATUS_SIZE]);
|
||||
|
||||
int intel_dp_get_training_pattern(struct intel_dp *intel_dp,
|
||||
u8 *recv);
|
||||
|
||||
int intel_dp_get_lane_count(struct intel_dp *intel_dp,
|
||||
u8 *recv);
|
||||
|
||||
int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
|
||||
u8 *recv);
|
||||
|
||||
void intel_prepare_ddi(void);
|
||||
void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp);
|
||||
|
||||
int gtt_poll(u32 reg, u32 mask, u32 value);
|
||||
void gtt_write(u32 reg, u32 data);
|
||||
@ -295,14 +101,8 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info *
|
||||
const struct i915_gpu_controller_info *
|
||||
intel_gma_get_controller_info(void);
|
||||
|
||||
int i915lightup(unsigned int physbase, unsigned int mmio,
|
||||
unsigned int gfx, unsigned int init_fb);
|
||||
int panel_lightup(struct intel_dp *dp, unsigned int init_fb);
|
||||
void *igd_make_opregion(void);
|
||||
|
||||
/* display.c */
|
||||
void compute_display_params(struct intel_dp *dp);
|
||||
|
||||
/* vbt.c */
|
||||
struct device;
|
||||
void
|
||||
|
||||
@ -114,159 +114,3 @@ void intel_prepare_ddi(void)
|
||||
|
||||
intel_prepare_ddi_buffers(PORT_E, use_fdi);
|
||||
}
|
||||
|
||||
static void intel_wait_ddi_buf_idle(int port)
|
||||
{
|
||||
uint32_t reg = DDI_BUF_CTL(port);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
udelay(1);
|
||||
if (gtt_read(reg) & DDI_BUF_IS_IDLE){
|
||||
printk(BIOS_SPEW, "%s: buf is idle (success)\n", __func__);
|
||||
return;
|
||||
}
|
||||
}
|
||||
printk(BIOS_ERR, "Timeout waiting for DDI BUF %d idle bit\n", port);
|
||||
}
|
||||
|
||||
|
||||
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port)
|
||||
{
|
||||
int wait = 0;
|
||||
uint32_t val;
|
||||
|
||||
if (gtt_read(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
|
||||
val = gtt_read(DDI_BUF_CTL(port));
|
||||
if (val & DDI_BUF_CTL_ENABLE) {
|
||||
val &= ~DDI_BUF_CTL_ENABLE;
|
||||
gtt_write(val,DDI_BUF_CTL(port));
|
||||
wait = 1;
|
||||
}
|
||||
|
||||
val = gtt_read(DP_TP_CTL(port));
|
||||
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
|
||||
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
||||
gtt_write(val,DP_TP_CTL(port));
|
||||
//POSTING_READ(DP_TP_CTL(port));
|
||||
|
||||
if (wait)
|
||||
intel_wait_ddi_buf_idle(port);
|
||||
}
|
||||
|
||||
val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
|
||||
DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
|
||||
if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
|
||||
val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
|
||||
gtt_write(val,DP_TP_CTL(port));
|
||||
//POSTING_READ(DP_TP_CTL(port));
|
||||
|
||||
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
|
||||
gtt_write(intel_dp->DP,DDI_BUF_CTL(port));
|
||||
//POSTING_READ(DDI_BUF_CTL(port));
|
||||
|
||||
udelay(600);
|
||||
}
|
||||
|
||||
u32 intel_ddi_calc_transcoder_flags(u32 pipe_bpp,
|
||||
enum port port,
|
||||
enum pipe pipe,
|
||||
int type,
|
||||
int lane_count,
|
||||
int pf_sz,
|
||||
u8 phsync,
|
||||
u8 pvsync)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
temp = TRANS_DDI_FUNC_ENABLE;
|
||||
temp |= TRANS_DDI_SELECT_PORT(port);
|
||||
|
||||
switch (pipe_bpp) {
|
||||
case 18:
|
||||
temp |= TRANS_DDI_BPC_6;
|
||||
break;
|
||||
case 24:
|
||||
temp |= TRANS_DDI_BPC_8;
|
||||
break;
|
||||
case 30:
|
||||
temp |= TRANS_DDI_BPC_10;
|
||||
break;
|
||||
case 36:
|
||||
temp |= TRANS_DDI_BPC_12;
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ERR, "Invalid pipe_bpp: %d, *** Initialization will not succeed ***\n", pipe_bpp);
|
||||
}
|
||||
|
||||
if (port == PORT_A) {
|
||||
switch (pipe) {
|
||||
case PIPE_A:
|
||||
if (pf_sz)
|
||||
temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
|
||||
else
|
||||
temp |= TRANS_DDI_EDP_INPUT_A_ON;
|
||||
break;
|
||||
case PIPE_B:
|
||||
temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
|
||||
break;
|
||||
case PIPE_C:
|
||||
temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ERR, "Invalid pipe %d\n", pipe);
|
||||
}
|
||||
}
|
||||
|
||||
if (phsync)
|
||||
temp |= TRANS_DDI_PHSYNC;
|
||||
|
||||
if (pvsync)
|
||||
temp |= TRANS_DDI_PVSYNC;
|
||||
|
||||
if (type == INTEL_OUTPUT_HDMI) {
|
||||
/* Need to understand when to set TRANS_DDI_MODE_SELECT_HDMI / TRANS_DDI_MODE_SELECT_DVI */
|
||||
} else if (type == INTEL_OUTPUT_ANALOG) {
|
||||
/* Set TRANS_DDI_MODE_SELECT_FDI with lane_count */
|
||||
} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
|
||||
type == INTEL_OUTPUT_EDP) {
|
||||
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
|
||||
|
||||
temp |= DDI_PORT_WIDTH(lane_count);
|
||||
} else {
|
||||
printk(BIOS_ERR, "Invalid type %d for pipe\n", type);
|
||||
}
|
||||
|
||||
return temp;
|
||||
}
|
||||
|
||||
enum transcoder intel_ddi_get_transcoder(enum port port,
|
||||
enum pipe pipe)
|
||||
{
|
||||
if (port == PORT_A)
|
||||
return TRANSCODER_EDP;
|
||||
return (enum transcoder)pipe;
|
||||
}
|
||||
|
||||
void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp)
|
||||
{
|
||||
u32 val = TRANS_MSA_SYNC_CLK;
|
||||
|
||||
switch (intel_dp->pipe_bits_per_pixel) {
|
||||
case 18:
|
||||
val |= TRANS_MSA_6_BPC;
|
||||
break;
|
||||
case 24:
|
||||
val |= TRANS_MSA_8_BPC;
|
||||
break;
|
||||
case 30:
|
||||
val |= TRANS_MSA_10_BPC;
|
||||
break;
|
||||
case 36:
|
||||
val |= TRANS_MSA_12_BPC;
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->pipe_bits_per_pixel);
|
||||
}
|
||||
gtt_write(TRANS_MSA_MISC(intel_dp->transcoder),val);
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user