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Update GPIO settings

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This commit is contained in:
Jeremy Soller
2019-05-10 10:19:02 -06:00
parent 6bbc98a1ef
commit 747364169f
1 changed files with 205 additions and 207 deletions
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412
src/mainboard/system76/cfl-h/gpio.h
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@@ -21,18 +21,16 @@
#ifndef __ACPI__
#define PAD_CFG_NC(pad) PAD_NC(pad, NONE)
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
// GPD
// Power Management
// NC
PAD_CFG_NC(GPD0),
PAD_NC(GPD0, NONE),
// AC_PRESENT
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
// NC
PAD_CFG_NC(GPD2),
PAD_NC(GPD2, NONE),
// PWR_BTN#
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
// SUSB#_PCH
@@ -40,111 +38,111 @@ static const struct pad_config gpio_table[] = {
// SUSC#_PCH
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPD6),
PAD_NC(GPD6, NONE),
// GPIO
// NC
PAD_CFG_NC(GPD7),
PAD_NC(GPD7, NONE),
// Power Management
// SUS_CLK_R
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPD9),
PAD_NC(GPD9, NONE),
// NC
PAD_CFG_NC(GPD10),
PAD_NC(GPD10, NONE),
// NC
PAD_CFG_NC(GPD11),
PAD_NC(GPD11, NONE),
// GPP_A
// LPC
// SB_KBCRST#
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
// LPC_AD0
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
// LPC_AD1
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
// LPC_AD2
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
// LPC_AD3
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
// LPC_FRAME#
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
// SERIRQ
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_A7),
PAD_NC(GPP_A7, NONE),
// PM_CLKRUN#
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
// PCLK_KBC
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_A10),
PAD_NC(GPP_A10, NONE),
// Power Management
// TODO: LAN_WAKEUP#
PAD_CFG_NC(GPP_A11),
PAD_CFG_GPI(GPP_A11, NONE, DEEP),
// NC
PAD_CFG_NC(GPP_A12),
PAD_NC(GPP_A12, NONE),
// SUSWARN#
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1),
// LPC
// NC
PAD_CFG_NC(GPP_A14),
PAD_NC(GPP_A14, NONE),
// Power Management
// SUS_PWR_ACK
PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1),
PAD_CFG_GPI(GPP_A15, NONE, DEEP),
// Clock Signals
// NC
PAD_CFG_NC(GPP_A16),
PAD_NC(GPP_A16, NONE),
// ISH
// NC
PAD_CFG_NC(GPP_A17),
PAD_NC(GPP_A17, NONE),
// SB_BLON
PAD_CFG_GPO(GPP_A18, 1, DEEP),
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
// NC
PAD_CFG_NC(GPP_A19),
PAD_NC(GPP_A19, NONE),
// NC
PAD_CFG_NC(GPP_A20),
PAD_NC(GPP_A20, NONE),
// NC
PAD_CFG_NC(GPP_A21),
PAD_NC(GPP_A21, NONE),
// SATA_PWR_EN
PAD_CFG_GPO(GPP_A22, 1, DEEP),
PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP),
// NC
PAD_CFG_NC(GPP_A23),
PAD_NC(GPP_A23, NONE),
// GPP_B
// GSPI
// TODO: TPM_PIRQ#
PAD_CFG_NC(GPP_B0),
PAD_NC(GPP_B0, NONE),
// NC
PAD_CFG_NC(GPP_B1),
PAD_NC(GPP_B1, NONE),
// Power Management
// NC
PAD_CFG_NC(GPP_B2),
PAD_NC(GPP_B2, NONE),
// CPU Misc
// NC
PAD_CFG_NC(GPP_B3),
PAD_NC(GPP_B3, NONE),
// TODO: EXTTS_SNI_DRV1
PAD_CFG_NC(GPP_B4),
PAD_NC(GPP_B4, NONE),
// Clock Signals
// NC
PAD_CFG_NC(GPP_B5),
PAD_NC(GPP_B5, NONE),
// NC
PAD_CFG_NC(GPP_B6),
PAD_NC(GPP_B6, NONE),
// NC
PAD_CFG_NC(GPP_B7),
PAD_NC(GPP_B7, NONE),
// NC
PAD_CFG_NC(GPP_B8),
PAD_NC(GPP_B8, NONE),
// NC
PAD_CFG_NC(GPP_B9),
PAD_NC(GPP_B9, NONE),
// LAN_CLKREQ#
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
@@ -154,7 +152,7 @@ static const struct pad_config gpio_table[] = {
// Power Management
// SLP_S0#
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B12, UP_20K, DEEP, NF1),
// PLT_RST#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
@@ -164,25 +162,25 @@ static const struct pad_config gpio_table[] = {
// GSPI
// NC
PAD_CFG_NC(GPP_B15),
PAD_NC(GPP_B15, NONE),
// NC
PAD_CFG_NC(GPP_B16),
PAD_NC(GPP_B16, NONE),
// NC
PAD_CFG_NC(GPP_B17),
PAD_NC(GPP_B17, NONE),
// LPSS_GSPI0_MOSI - strap for no reboot mode
PAD_CFG_NC(GPP_B18),
PAD_NC(GPP_B18, NONE),
// NC
PAD_CFG_NC(GPP_B19),
PAD_NC(GPP_B19, NONE),
// NC
PAD_CFG_NC(GPP_B20),
PAD_NC(GPP_B20, NONE),
// NC
PAD_CFG_NC(GPP_B21),
PAD_NC(GPP_B21, NONE),
// LPSS_GSPI1_MOSI - strap for booting from SPI or LPC
PAD_CFG_NC(GPP_B22),
PAD_NC(GPP_B22, NONE),
// SMBUS
// PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode
PAD_CFG_NC(GPP_B23),
PAD_NC(GPP_B23, NONE),
// GPP_C
// SMBUS
@@ -191,70 +189,70 @@ static const struct pad_config gpio_table[] = {
// SMB_DATA
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_C2),
PAD_NC(GPP_C2, NONE),
// NC
PAD_CFG_NC(GPP_C3),
PAD_NC(GPP_C3, NONE),
// NC
PAD_CFG_NC(GPP_C4),
PAD_NC(GPP_C4, NONE),
// NC
PAD_CFG_NC(GPP_C5),
PAD_NC(GPP_C5, NONE),
// NC
PAD_CFG_NC(GPP_C6),
PAD_NC(GPP_C6, NONE),
// NC
PAD_CFG_NC(GPP_C7),
PAD_NC(GPP_C7, NONE),
// UART
// NC
PAD_CFG_NC(GPP_C8),
PAD_NC(GPP_C8, NONE),
// TODO: CNVI_DET#
PAD_CFG_NC(GPP_C9),
PAD_NC(GPP_C9, NONE),
// NC
PAD_CFG_NC(GPP_C10),
PAD_NC(GPP_C10, NONE),
// NC
PAD_CFG_NC(GPP_C11),
PAD_NC(GPP_C11, NONE),
// NC
PAD_CFG_NC(GPP_C12),
PAD_NC(GPP_C12, NONE),
// NC
PAD_CFG_NC(GPP_C13),
PAD_NC(GPP_C13, NONE),
// NC
PAD_CFG_NC(GPP_C14),
PAD_NC(GPP_C14, NONE),
// NC
PAD_CFG_NC(GPP_C15),
PAD_NC(GPP_C15, NONE),
// I2C
// I2C_SCL_TP
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
// I2C_SDA_TP
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
// NC
PAD_CFG_NC(GPP_C18),
PAD_NC(GPP_C18, NONE),
// NC
PAD_CFG_NC(GPP_C19),
PAD_NC(GPP_C19, NONE),
// UART
// UART2_RXD
PAD_CFG_NC(GPP_C20), //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
// UART2_TXD
PAD_CFG_NC(GPP_C21), //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_C22),
PAD_NC(GPP_C22, NONE),
// NC
PAD_CFG_NC(GPP_C23),
PAD_NC(GPP_C23, NONE),
// GPP_D
// SPI
// NC
PAD_CFG_NC(GPP_D0),
PAD_NC(GPP_D0, NONE),
// NC
PAD_CFG_NC(GPP_D1),
PAD_NC(GPP_D1, NONE),
// NC
PAD_CFG_NC(GPP_D2),
PAD_NC(GPP_D2, NONE),
// NC
PAD_CFG_NC(GPP_D3),
PAD_NC(GPP_D3, NONE),
// I2C
// NC
PAD_CFG_NC(GPP_D4),
PAD_NC(GPP_D4, NONE),
// CNVI
// CNVI_RF_RST#
@@ -262,72 +260,72 @@ static const struct pad_config gpio_table[] = {
// XTAL_CLKREQ
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
// NC
PAD_CFG_NC(GPP_D7),
PAD_NC(GPP_D7, NONE),
// NC
PAD_CFG_NC(GPP_D8),
PAD_NC(GPP_D8, NONE),
// ISH
// NC
PAD_CFG_NC(GPP_D9),
PAD_NC(GPP_D9, NONE),
// NC
PAD_CFG_NC(GPP_D10),
PAD_NC(GPP_D10, NONE),
// NC
PAD_CFG_NC(GPP_D11),
PAD_NC(GPP_D11, NONE),
// NC
PAD_CFG_NC(GPP_D12),
PAD_NC(GPP_D12, NONE),
// NC
PAD_CFG_NC(GPP_D13),
PAD_NC(GPP_D13, NONE),
// NC
PAD_CFG_NC(GPP_D14),
PAD_NC(GPP_D14, NONE),
// NC
PAD_CFG_NC(GPP_D15),
PAD_NC(GPP_D15, NONE),
// NC
PAD_CFG_NC(GPP_D16),
PAD_NC(GPP_D16, NONE),
// DMIC
// NC
PAD_CFG_NC(GPP_D17),
PAD_NC(GPP_D17, NONE),
// NC
PAD_CFG_NC(GPP_D18),
PAD_NC(GPP_D18, NONE),
// NC
PAD_CFG_NC(GPP_D19),
PAD_NC(GPP_D19, NONE),
// NC
PAD_CFG_NC(GPP_D20),
PAD_NC(GPP_D20, NONE),
// SPI
// NC
PAD_CFG_NC(GPP_D21),
PAD_NC(GPP_D21, NONE),
// NC
PAD_CFG_NC(GPP_D22),
PAD_NC(GPP_D22, NONE),
// ISH
// NC
PAD_CFG_NC(GPP_D23),
PAD_NC(GPP_D23, NONE),
// GPP_E
// SATA
// NC
PAD_CFG_NC(GPP_E0),
PAD_NC(GPP_E0, NONE),
// SATAGP1
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1),
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_E2),
PAD_NC(GPP_E2, NONE),
// CPU Misc
// TODO: EXTTS_SNI_DRV0
PAD_CFG_NC(GPP_E3),
PAD_NC(GPP_E3, NONE),
// SATA
// DEVSLP0
PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E4, UP_20K, DEEP, NF1),
// DEVSLP1
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E5, UP_20K, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_E6),
PAD_NC(GPP_E6, NONE),
// CPU Misc
// TODO: TP_ATTN#
PAD_CFG_NC(GPP_E7),
PAD_NC(GPP_E7, NONE),
// SATA
// SATA_LED#
@@ -335,58 +333,58 @@ static const struct pad_config gpio_table[] = {
// USB2
// NC
PAD_CFG_NC(GPP_E9),
PAD_NC(GPP_E9, NONE),
// NC
PAD_CFG_NC(GPP_E10),
PAD_NC(GPP_E10, NONE),
// NC
PAD_CFG_NC(GPP_E11),
PAD_NC(GPP_E11, NONE),
// NC
PAD_CFG_NC(GPP_E12),
PAD_NC(GPP_E12, NONE),
// GPP_F
// SATA
// NC
PAD_CFG_NC(GPP_F0),
PAD_NC(GPP_F0, NONE),
// NC
PAD_CFG_NC(GPP_F1),
PAD_NC(GPP_F1, NONE),
// NC
PAD_CFG_NC(GPP_F2),
PAD_NC(GPP_F2, NONE),
// NC
PAD_CFG_NC(GPP_F3),
PAD_NC(GPP_F3, NONE),
// NC
PAD_CFG_NC(GPP_F4),
// TODO: KBLED_DET
PAD_CFG_NC(GPP_F5),
// TODO: LIGHT_KB_DET#
PAD_CFG_NC(GPP_F6),
PAD_NC(GPP_F4, NONE),
// KBLED_DET
PAD_CFG_GPI(GPP_F5, NONE, DEEP),
// LIGHT_KB_DET#
PAD_CFG_GPI(GPP_F6, NONE, DEEP),
// NC
PAD_CFG_NC(GPP_F7),
PAD_NC(GPP_F7, NONE),
// NC
PAD_CFG_NC(GPP_F8),
PAD_NC(GPP_F8, NONE),
// NC
PAD_CFG_NC(GPP_F9),
PAD_NC(GPP_F9, NONE),
// BIOS_REC - strap for bios recovery enable
PAD_CFG_NC(GPP_F10),
PAD_NC(GPP_F10, NONE),
// PCH_RSVD - unused strap
PAD_CFG_NC(GPP_F11),
PAD_NC(GPP_F11, NONE),
// MFG_MODE - strap for manufacturing mode
PAD_CFG_NC(GPP_F12),
PAD_NC(GPP_F12, NONE),
// TODO: GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx
PAD_CFG_NC(GPP_F13),
PAD_NC(GPP_F13, NONE),
// Power Management
// TODO: H_SKTOCC_N
PAD_CFG_NC(GPP_F14),
// H_SKTOCC_N
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP),
// USB2
// NC
PAD_CFG_NC(GPP_F15),
PAD_NC(GPP_F15, NONE),
// NC
PAD_CFG_NC(GPP_F16),
PAD_NC(GPP_F16, NONE),
// NC
PAD_CFG_NC(GPP_F17),
PAD_NC(GPP_F17, NONE),
// NC
PAD_CFG_NC(GPP_F18),
PAD_NC(GPP_F18, NONE),
// Display Signals
// NB_ENAVDD
@@ -396,143 +394,143 @@ static const struct pad_config gpio_table[] = {
// EDP_BRIGHTNESS
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
// TODO: DGPU_RST#_PCH
PAD_CFG_GPO(GPP_F22, 0, DEEP),
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST),
// TODO: DGPU_PWR_EN
PAD_CFG_GPO(GPP_F23, 0, DEEP),
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP),
// GPP_G
// SD
// TODO: BOARD_ID1
PAD_CFG_NC(GPP_G0),
// TODO: BOARD_ID2
PAD_CFG_NC(GPP_G1),
// TODO: TPM_DET
PAD_CFG_NC(GPP_G2),
// BOARD_ID1
PAD_CFG_GPI(GPP_G0, NONE, DEEP),
// BOARD_ID2
PAD_CFG_GPI(GPP_G1, NONE, DEEP),
// TPM_DET
PAD_CFG_GPI(GPP_G2, NONE, DEEP),
// TODO: GPIO4_1V8_MAIN_EN_R
PAD_CFG_NC(GPP_G3),
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
// NC
PAD_CFG_NC(GPP_G4),
PAD_NC(GPP_G4, NONE),
// NC
PAD_CFG_NC(GPP_G5),
PAD_NC(GPP_G5, NONE),
// NC
PAD_CFG_NC(GPP_G6),
PAD_NC(GPP_G6, NONE),
// NC
PAD_CFG_NC(GPP_G7),
PAD_NC(GPP_G7, NONE),
// GPP_H
// Clock Signals
// WLAN_CLKREQ#
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_H1),
PAD_NC(GPP_H1, NONE),
// PEG_CLKREQ#
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_H3),
PAD_NC(GPP_H3, NONE),
// SSD_CLKREQ#
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
// SSD2_CLKREQ#
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_H6),
PAD_NC(GPP_H6, NONE),
// NC
PAD_CFG_NC(GPP_H7),
PAD_NC(GPP_H7, NONE),
// NC
PAD_CFG_NC(GPP_H8),
PAD_NC(GPP_H8, NONE),
// NC
PAD_CFG_NC(GPP_H9),
PAD_NC(GPP_H9, NONE),
// SMBUS
// NC
PAD_CFG_NC(GPP_H10),
PAD_NC(GPP_H10, NONE),
// NC
PAD_CFG_NC(GPP_H11),
PAD_NC(GPP_H11, NONE),
// GPP_H_12 - strap for ESPI flash sharing mode
PAD_CFG_NC(GPP_H12),
PAD_NC(GPP_H12, NONE),
// NC
PAD_CFG_NC(GPP_H13),
PAD_NC(GPP_H13, NONE),
// NC
PAD_CFG_NC(GPP_H14),
PAD_NC(GPP_H14, NONE),
// NC
PAD_CFG_NC(GPP_H15),
PAD_NC(GPP_H15, NONE),
// NC
PAD_CFG_NC(GPP_H16),
PAD_NC(GPP_H16, NONE),
// NC
PAD_CFG_NC(GPP_H17),
PAD_NC(GPP_H17, NONE),
// NC
PAD_CFG_NC(GPP_H18),
PAD_NC(GPP_H18, NONE),
// ISH
// NC
PAD_CFG_NC(GPP_H19),
PAD_NC(GPP_H19, NONE),
// NC
PAD_CFG_NC(GPP_H20),
PAD_NC(GPP_H20, NONE),
// NC
PAD_CFG_NC(GPP_H21),
PAD_NC(GPP_H21, NONE),
// NC
PAD_CFG_NC(GPP_H22),
PAD_NC(GPP_H22, NONE),
// GPIO
// NC
PAD_CFG_NC(GPP_H23),
PAD_NC(GPP_H23, NONE),
// GPP_I
// Display Signals
// NC
PAD_CFG_NC(GPP_I0),
PAD_NC(GPP_I0, NONE),
// HDMI_HPD
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I1, NATIVE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_I2),
PAD_NC(GPP_I2, NONE),
// MDP_E_HPD
PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
// EDP_HPD
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_I5),
PAD_NC(GPP_I5, NONE),
// NC
PAD_CFG_NC(GPP_I6),
PAD_NC(GPP_I6, NONE),
// HDMI_CTRLCLK
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
// HDMI_CTRLDATA
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
// NC
PAD_CFG_NC(GPP_I9),
PAD_NC(GPP_I9, NONE),
// NC
PAD_CFG_NC(GPP_I10),
PAD_NC(GPP_I10, NONE),
// PCIE
// TODO: H_SKTOCC_N
PAD_CFG_NC(GPP_I11),
PAD_NC(GPP_I11, NONE),
// NC
PAD_CFG_NC(GPP_I12),
PAD_NC(GPP_I12, NONE),
// NC
PAD_CFG_NC(GPP_I13),
PAD_NC(GPP_I13, NONE),
// NC
PAD_CFG_NC(GPP_I14),
PAD_NC(GPP_I14, NONE),
// GPP_J
// CNVI
// CNVI_GNSS_PA_BLANKING
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J0, NATIVE, DEEP, NF1),
// Power Management
// NC
PAD_CFG_NC(GPP_J1),
PAD_NC(GPP_J1, NONE),
// GPIO
// NC
PAD_CFG_NC(GPP_J2),
PAD_NC(GPP_J2, NONE),
// NC
PAD_CFG_NC(GPP_J3),
PAD_NC(GPP_J3, NONE),
// CNVI
// CNVI_BRI_DT
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J4, NATIVE, DEEP, NF1),
// CNVI_BRI_RSP
PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1),
// CNVI_RGI_DT
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_J6, NONE, PLTRST, NF1),
// CNVI_RGI_RSP
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1),
// CNVI_MFUART2_RXD
@@ -542,75 +540,75 @@ static const struct pad_config gpio_table[] = {
// GPIO
// NC
PAD_CFG_NC(GPP_J10),
PAD_NC(GPP_J10, NONE),
// A4WP
// NC
PAD_CFG_NC(GPP_J11),
PAD_NC(GPP_J11, NONE),
// GPP_K
// GPIO
// NC
PAD_CFG_NC(GPP_K0),
PAD_NC(GPP_K0, NONE),
// NC
PAD_CFG_NC(GPP_K1),
PAD_NC(GPP_K1, NONE),
// NC
PAD_CFG_NC(GPP_K2),
PAD_NC(GPP_K2, NONE),
// SCI#
PAD_CFG_GPI_SCI_LOW(GPP_K3, NONE, DEEP, LEVEL),
PAD_CFG_GPI_SCI_LOW(GPP_K3, UP_20K, DEEP, LEVEL),
// NC
PAD_CFG_NC(GPP_K4),
PAD_NC(GPP_K4, NONE),
// NC
PAD_CFG_NC(GPP_K5),
PAD_NC(GPP_K5, NONE),
// SWI#
PAD_CFG_GPI_SCI_LOW(GPP_K6, NONE, DEEP, LEVEL),
PAD_CFG_GPI_SCI_LOW(GPP_K6, UP_20K, DEEP, LEVEL),
// NC
PAD_CFG_NC(GPP_K7),
// SATA_M2_PWR_EN1
PAD_CFG_GPO(GPP_K8, 1, DEEP),
// SATA_M2_PWR_EN2
PAD_CFG_GPO(GPP_K9, 1, DEEP),
PAD_NC(GPP_K7, NONE),
// TODO: SATA_M2_PWR_EN1
PAD_CFG_GPI(GPP_K8, NONE, DEEP),
// TODO: SATA_M2_PWR_EN2
PAD_CFG_GPI(GPP_K9, NONE, DEEP),
// NC
PAD_CFG_NC(GPP_K10),
PAD_NC(GPP_K10, NONE),
// NC
PAD_CFG_NC(GPP_K11),
PAD_NC(GPP_K11, NONE),
// GSX
// NC
PAD_CFG_NC(GPP_K12),
PAD_NC(GPP_K12, NONE),
// NC
PAD_CFG_NC(GPP_K13),
PAD_NC(GPP_K13, NONE),
// NC
PAD_CFG_NC(GPP_K14),
PAD_NC(GPP_K14, NONE),
// NC
PAD_CFG_NC(GPP_K15),
PAD_NC(GPP_K15, NONE),
// NC
PAD_CFG_NC(GPP_K16),
PAD_NC(GPP_K16, NONE),
// GPIO
// NC
PAD_CFG_NC(GPP_K17),
PAD_NC(GPP_K17, NONE),
// NC
PAD_CFG_NC(GPP_K18),
PAD_NC(GPP_K18, NONE),
// SMI#
_PAD_CFG_STRUCT(GPP_K19, 0x42840100, 0x0),
_PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000),
// TODO: GPU_EVENT#
PAD_CFG_NC(GPP_K20),
PAD_CFG_GPI(GPP_K20, NONE, DEEP),
// TODO: GC6_FB_EN_PCH
PAD_CFG_NC(GPP_K21),
PAD_CFG_GPI(GPP_K21, NONE, DEEP),
// TODO: DGPU_PWRGD_R
PAD_CFG_NC(GPP_K22),
_PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000),
// NC
PAD_CFG_NC(GPP_K23),
PAD_NC(GPP_K23, NONE),
};
/* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
// UART2
// UART2_RXD
PAD_CFG_NC(GPP_C20), //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
// UART2_TXD
PAD_CFG_NC(GPP_C21), //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
};
#endif