kunimitsu: Clean up mainboard code to match glados
Clean up the intel/kunimitsu mainboard code to match the code and cleanups in glados. Many of these are trivial changes that do not impact things in a meaningful way but will make it easier to diff the code and keep the mainboards in sync. - use relative path for mainboard includes to make porting easier - fix trivial style issues to match glados so diffs are clean - pull GPIO configuration into gpio.h and use from there - remove thermal.h as it is not used on this board - make info message BIOS_INFO instead of BIOS_ERR - add support for SPD manufacturer and part number in SMBIOS BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297752 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
committed by
Patrick Georgi
parent
963bfa7a0f
commit
74b964ec4a
@ -18,7 +18,6 @@
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* Foundation, Inc.
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* Foundation, Inc.
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*/
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*/
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/* CPU */
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#define DPTF_CPU_PASSIVE 80
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#define DPTF_CPU_PASSIVE 80
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#define DPTF_CPU_CRITICAL 90
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#define DPTF_CPU_CRITICAL 90
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#define DPTF_CPU_ACTIVE_AC0 90
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#define DPTF_CPU_ACTIVE_AC0 90
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@ -53,9 +52,6 @@ Name (CHPS, Package () {
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Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
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Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
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})
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})
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/* Mainboard specific _PDL is 1GHz */
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Name (MPDL, 8)
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Name (DTRT, Package () {
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
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Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
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@ -20,20 +20,22 @@
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#include "../gpio.h"
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#include "../gpio.h"
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#define BOARD_TRACKPAD_IRQ 0x33
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#define BOARD_TOUCHPAD_I2C_ADDR 0x15
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#define BOARD_TOUCHSCREEN_IRQ 0x1f
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#define BOARD_TOUCHPAD_IRQ TOUCHPAD_INT_L
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#define BOARD_TRACKPAD_I2C_ADDR 0x15
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#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10
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#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10
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#define BOARD_TOUCHSCREEN_IRQ TOUCHSCREEN_INT_L
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#define BOARD_LEFT_SSM4567_I2C_ADDR 0x34
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#define BOARD_RIGHT_SSM4567_I2C_ADDR 0x35
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#define BOARD_HP_MIC_CODEC_I2C_ADDR 0x1a
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#define BOARD_AUDIO_CODEC_I2C_ADDR 0x1A
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#define BOARD_HP_MIC_CODEC_IRQ MIC_INT_L
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#define BOARD_LEFT_SPEAKER_AMP_I2C_ADDR 0x34
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#define BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR 0x35
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Scope (\_SB)
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Scope (\_SB)
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{
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{
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Device (LID0)
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Device (LID0)
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{
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{
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Name (_HID, EisaId("PNP0C0D"))
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Name (_HID, EisaId ("PNP0C0D"))
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Method (_LID, 0)
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Method (_LID, 0)
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{
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{
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Return (\_SB.PCI0.LPCB.EC0.LIDS)
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Return (\_SB.PCI0.LPCB.EC0.LIDS)
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@ -44,9 +46,10 @@ Scope (\_SB)
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Device (PWRB)
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Device (PWRB)
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{
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{
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Name (_HID, EisaId("PNP0C0C"))
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Name (_HID, EisaId ("PNP0C0C"))
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}
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}
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}
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}
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/*
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/*
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* LPC Trusted Platform Module
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* LPC Trusted Platform Module
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*/
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*/
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@ -57,13 +60,15 @@ Scope (\_SB.PCI0.LPCB)
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Scope (\_SB.PCI0.I2C0)
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Scope (\_SB.PCI0.I2C0)
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{
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{
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Device (ETSA)
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/* Touchscreen */
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Device (ELTS)
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{
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{
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Name (_HID, "ELAN0001")
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Name (_HID, "ELAN0001")
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Name (_DDN, "ELAN Touchscreen")
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Name (_DDN, "Elan Touchscreen")
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Name (_UID, 5)
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Name (_UID, 1)
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Name (ISTP, 0) /* TouchScreen */
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Name (_S0W, 4)
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Name (_CRS, ResourceTemplate()
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Name (_CRS, ResourceTemplate ()
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{
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{
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I2cSerialBus (
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I2cSerialBus (
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BOARD_TOUCHSCREEN_I2C_ADDR,
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BOARD_TOUCHSCREEN_I2C_ADDR,
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@ -72,11 +77,13 @@ Scope (\_SB.PCI0.I2C0)
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AddressingMode7Bit,
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AddressingMode7Bit,
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"\\_SB.PCI0.I2C0",
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"\\_SB.PCI0.I2C0",
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)
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)
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Interrupt (ResourceConsumer, Edge, ActiveLow) {
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Interrupt (ResourceConsumer, Edge, ActiveLow)
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{
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BOARD_TOUCHSCREEN_IRQ
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BOARD_TOUCHSCREEN_IRQ
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}
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}
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})
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})
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Method (_STA, 0, NotSerialized)
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Method (_STA)
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{
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{
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Return (0xF)
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Return (0xF)
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}
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}
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@ -85,18 +92,18 @@ Scope (\_SB.PCI0.I2C0)
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Scope (\_SB.PCI0.I2C1)
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Scope (\_SB.PCI0.I2C1)
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{
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{
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Device (ELAN)
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/* Touchpad */
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Device (ELTP)
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{
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{
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Name (_HID, "ELAN0000")
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Name (_HID, "ELAN0000")
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Name (_DDN, "Elan Touchpad")
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Name (_DDN, "Elan Touchpad")
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Name (_UID, 3)
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Name (_UID, 1)
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/* Allow device to power off in S0 */
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Name (_S0W, 4)
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Name (_S0W, 4)
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Name (ISTP, 1) /* TouchPad */
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Name (_CRS, ResourceTemplate()
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Name (_CRS, ResourceTemplate ()
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{
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{
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I2cSerialBus (
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I2cSerialBus (
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BOARD_TRACKPAD_I2C_ADDR,
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BOARD_TOUCHPAD_I2C_ADDR,
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ControllerInitiated,
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ControllerInitiated,
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400000,
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400000,
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AddressingMode7Bit,
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AddressingMode7Bit,
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@ -104,9 +111,10 @@ Scope (\_SB.PCI0.I2C1)
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)
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)
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Interrupt (ResourceConsumer, Edge, ActiveLow)
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Interrupt (ResourceConsumer, Edge, ActiveLow)
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{
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{
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BOARD_TRACKPAD_IRQ
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BOARD_TOUCHPAD_IRQ
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}
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}
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})
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})
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Method (_STA)
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Method (_STA)
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{
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{
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Return (0xF)
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Return (0xF)
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@ -116,68 +124,45 @@ Scope (\_SB.PCI0.I2C1)
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Scope (\_SB.PCI0.I2C4)
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Scope (\_SB.PCI0.I2C4)
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{
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{
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// LEFT SSM4567 I2c ADDR 0x34
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/* Headphone Codec */
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Device (LSPK)
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Device (HPMC)
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{
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Name (_HID, "INT343B")
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Name (_CID, "INT343B")
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Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec")
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Name (_UID, 1)
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Name (_CRS, ResourceTemplate()
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{
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I2cSerialBus (
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BOARD_LEFT_SSM4567_I2C_ADDR,
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ControllerInitiated,
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400000,
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AddressingMode7Bit,
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"\\_SB.PCI0.I2C4",
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)
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})
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Method (_STA, 0, NotSerialized)
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{
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Return (0xF) // I2S Codec ADI LEFT SSM4567 Enabled
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}
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} // Device (LSPK)
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// RIGHT SSM4567 I2C ADDR 0x35
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Device (RSPK)
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{
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Name (_HID, "INT343B")
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Name (_CID, "INT343B")
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Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec")
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Name (_UID, 2)
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Name (_CRS, ResourceTemplate()
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{
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I2cSerialBus (
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BOARD_RIGHT_SSM4567_I2C_ADDR,
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ControllerInitiated,
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400000,
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AddressingMode7Bit,
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"\\_SB.PCI0.I2C4",
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)
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})
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Method (_STA, 0, NotSerialized)
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{
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Return (0xF) // I2S Codec ADI RIGHT SSM4567 Enabled
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}
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} // Device (RSPK)
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// Nuvoton NAU88L25 (I2SC = 2)
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Device (HDAC)
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{
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{
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Name (_HID, "10508825")
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Name (_HID, "10508825")
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Name (_CID, "10508825")
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Name (_DDN, "NAU88L25 Codec")
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Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec")
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Name (_UID, 1)
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Name (_UID, 1)
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Name (_CRS, ResourceTemplate()
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Name (_CRS, ResourceTemplate()
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{
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{
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I2cSerialBus (
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I2cSerialBus (
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BOARD_AUDIO_CODEC_I2C_ADDR,
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BOARD_HP_MIC_CODEC_I2C_ADDR,
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ControllerInitiated,
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400000,
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AddressingMode7Bit,
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"\\_SB.PCI0.I2C4",
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)
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Interrupt (ResourceConsumer, Edge, ActiveLow)
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{
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BOARD_HP_MIC_CODEC_IRQ
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}
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})
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Method (_STA)
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{
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Return (0xF)
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}
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}
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/* Left Speaker Amp */
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Device (SPKL)
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{
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Name (_HID, "INT343B")
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Name (_DDN, "SSM4567 Speaker Amp")
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Name (_UID, 0)
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Name (_CRS, ResourceTemplate()
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{
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I2cSerialBus (
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BOARD_LEFT_SPEAKER_AMP_I2C_ADDR,
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ControllerInitiated,
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ControllerInitiated,
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400000,
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400000,
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AddressingMode7Bit,
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AddressingMode7Bit,
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@ -185,11 +170,33 @@ Scope (\_SB.PCI0.I2C4)
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)
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)
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})
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})
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Method (_STA, 0, NotSerialized)
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Method (_STA)
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{
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{
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Return (0xF) // I2S Codec Enabled
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Return (0xF)
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}
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}
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} // Device (HDAC)
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}
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/* Right Speaker Amp */
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Device (SPKR)
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{
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Name (_HID, "INT343B")
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Name (_DDN, "SSM4567 Speaker Amp")
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Name (_UID, 1)
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Name (_CRS, ResourceTemplate()
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{
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I2cSerialBus (
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BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR,
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ControllerInitiated,
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400000,
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AddressingMode7Bit,
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"\\_SB.PCI0.I2C4",
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)
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})
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Method (_STA)
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{
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Return (0xF)
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}
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}
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}
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}
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@ -18,7 +18,7 @@
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*/
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*/
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/* mainboard configuration */
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/* mainboard configuration */
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#include <mainboard/intel/kunimitsu/ec.h>
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#include "../ec.h"
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#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
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#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
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#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
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#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
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@ -18,36 +18,14 @@
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* Foundation, Inc.
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* Foundation, Inc.
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*/
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*/
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#include <types.h>
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#include <string.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <arch/ioapic.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/cpu.h>
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#include <soc/acpi.h>
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#include <soc/acpi.h>
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#include <soc/nvs.h>
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#include <soc/nvs.h>
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#include "thermal.h"
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extern const unsigned char AmlCode[];
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void acpi_create_gnvs(global_nvs_t *gnvs)
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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{
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acpi_init_gnvs(gnvs);
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acpi_init_gnvs(gnvs);
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/* Disable USB ports in S5 */
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gnvs->s5u0 = 0;
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gnvs->tmps = TEMPERATURE_SENSOR_ID;
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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gnvs->tmax = MAX_TEMPERATURE;
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gnvs->dpte = 1;
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}
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}
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unsigned long acpi_fill_madt(unsigned long current)
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unsigned long acpi_fill_madt(unsigned long current)
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@ -22,11 +22,13 @@
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#include <console/console.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <ec/google/chromeec/ec.h>
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#include <rules.h>
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#include <gpio.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <soc/gpio.h>
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#include <string.h>
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#include <string.h>
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#include <ec/google/chromeec/ec.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "gpio.h"
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#include "gpio.h"
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#include "ec.h"
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#include "ec.h"
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@ -16,6 +16,9 @@ chip soc/intel/skylake
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# EC host command range is in 0x800-0x8ff
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# EC host command range is in 0x800-0x8ff
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register "gen1_dec" = "0x00fc0801"
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register "gen1_dec" = "0x00fc0801"
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# Enable DPTF
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register "dptf_enable" = "1"
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# FSP Configuration
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableLan" = "0"
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@ -43,7 +43,8 @@ DefinitionBlock(
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#include <soc/intel/skylake/acpi/systemagent.asl>
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#include <soc/intel/skylake/acpi/systemagent.asl>
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#include <soc/intel/skylake/acpi/pch.asl>
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#include <soc/intel/skylake/acpi/pch.asl>
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}
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}
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// Thermal handler
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// Dynamic Platform Thermal Framework
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#include "acpi/dptf.asl"
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#include "acpi/dptf.asl"
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}
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}
|
||||||
|
|
||||||
|
@ -25,11 +25,9 @@
|
|||||||
|
|
||||||
void mainboard_ec_init(void)
|
void mainboard_ec_init(void)
|
||||||
{
|
{
|
||||||
printk(BIOS_DEBUG, "mainboard_ec_init\n");
|
printk(BIOS_DEBUG, "mainboard: EC init\n");
|
||||||
post_code(0xf0);
|
|
||||||
|
|
||||||
/* Restore SCI event mask on resume. */
|
if (acpi_is_wakeup_s3()) {
|
||||||
if (acpi_slp_type == 3) {
|
|
||||||
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
|
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
|
||||||
MAINBOARD_EC_S3_WAKE_EVENTS);
|
MAINBOARD_EC_S3_WAKE_EVENTS);
|
||||||
|
|
||||||
@ -39,10 +37,8 @@ void mainboard_ec_init(void)
|
|||||||
/* Clear pending events */
|
/* Clear pending events */
|
||||||
while (google_chromeec_get_event() != 0)
|
while (google_chromeec_get_event() != 0)
|
||||||
;
|
;
|
||||||
/*
|
|
||||||
* Set SCI mask.OS may not generate SMI event to set
|
/* Restore SCI event mask */
|
||||||
* this on S3 resume.
|
|
||||||
*/
|
|
||||||
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
|
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
|
||||||
} else {
|
} else {
|
||||||
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
|
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
|
||||||
@ -51,5 +47,4 @@ void mainboard_ec_init(void)
|
|||||||
|
|
||||||
/* Clear wake event mask */
|
/* Clear wake event mask */
|
||||||
google_chromeec_set_wake_mask(0);
|
google_chromeec_set_wake_mask(0);
|
||||||
post_code(0xf1);
|
|
||||||
}
|
}
|
||||||
|
@ -47,6 +47,5 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
|
|||||||
|
|
||||||
acpi_fill_in_fadt(fadt);
|
acpi_fill_in_fadt(fadt);
|
||||||
|
|
||||||
header->checksum =
|
header->checksum = acpi_checksum((void *) fadt, header->length);
|
||||||
acpi_checksum((void *) fadt, header->length);
|
|
||||||
}
|
}
|
||||||
|
@ -29,8 +29,21 @@
|
|||||||
|
|
||||||
/* BIOS Flash Write Protect */
|
/* BIOS Flash Write Protect */
|
||||||
#define GPIO_PCH_WP GPP_C23
|
#define GPIO_PCH_WP GPP_C23
|
||||||
|
|
||||||
|
/* Memory configuration board straps */
|
||||||
|
#define GPIO_MEM_CONFIG_0 GPP_C12
|
||||||
|
#define GPIO_MEM_CONFIG_1 GPP_C13
|
||||||
|
#define GPIO_MEM_CONFIG_2 GPP_C14
|
||||||
|
#define GPIO_MEM_CONFIG_3 GPP_C15
|
||||||
|
|
||||||
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
|
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
|
||||||
#define GPE_EC_WAKE GPE0_LAN_WAK
|
#define GPE_EC_WAKE GPE0_LAN_WAK
|
||||||
|
|
||||||
|
/* Input device interrupt configuration */
|
||||||
|
#define TOUCHPAD_INT_L GPP_B3_IRQ
|
||||||
|
#define TOUCHSCREEN_INT_L GPP_E7_IRQ
|
||||||
|
#define MIC_INT_L GPP_F10_IRQ
|
||||||
|
|
||||||
/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */
|
/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */
|
||||||
#define EC_SCI_GPI GPE0_DW2_16
|
#define EC_SCI_GPI GPE0_DW2_16
|
||||||
#define EC_SMI_GPI GPP_E15
|
#define EC_SMI_GPI GPP_E15
|
||||||
|
@ -25,24 +25,22 @@
|
|||||||
|
|
||||||
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
||||||
{
|
{
|
||||||
/* DQ byte map for kunimitsu board */
|
/* DQ byte map */
|
||||||
const u8 dq_map[2][12] = {
|
const u8 dq_map[2][12] = {
|
||||||
{0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
|
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
|
||||||
0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00},
|
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
|
||||||
{0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 ,
|
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
|
||||||
0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} };
|
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
|
||||||
/* DQS CPU<>DRAM map for kunimitsu board */
|
/* DQS CPU<>DRAM map */
|
||||||
const u8 dqs_map[2][8] = {
|
const u8 dqs_map[2][8] = {
|
||||||
{0, 1, 3, 2, 6, 5, 4, 7},
|
{ 0, 1, 3, 2, 6, 5, 4, 7 },
|
||||||
{2, 3, 0, 1, 6, 7, 4, 5} };
|
{ 2, 3, 0, 1, 6, 7, 4, 5 } };
|
||||||
|
|
||||||
/* Rcomp resistor*/
|
/* Rcomp resistor */
|
||||||
const u16 RcompResistor[3] = {200, 81, 162 };
|
const u16 RcompResistor[3] = { 200, 81, 162 };
|
||||||
|
|
||||||
/* Rcomp target*/
|
/* Rcomp target */
|
||||||
const u16 RcompTarget[5] = {100, 40, 40, 23, 40};
|
const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
|
||||||
|
|
||||||
pei_data->ec_present = 1;
|
|
||||||
|
|
||||||
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
|
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
|
||||||
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
|
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
|
||||||
|
@ -11,6 +11,10 @@
|
|||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
* GNU General Public License for more details.
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <soc/ramstage.h>
|
#include <soc/ramstage.h>
|
||||||
|
@ -21,13 +21,12 @@
|
|||||||
|
|
||||||
#include <cbfs.h>
|
#include <cbfs.h>
|
||||||
#include <console/console.h>
|
#include <console/console.h>
|
||||||
|
#include <memory_info.h>
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <ec/google/chromeec/ec.h>
|
#include <ec/google/chromeec/ec.h>
|
||||||
#include <soc/cpu.h>
|
|
||||||
#include <soc/gpio.h>
|
#include <soc/gpio.h>
|
||||||
#include <soc/pei_data.h>
|
#include <soc/pei_data.h>
|
||||||
#include <soc/pei_wrapper.h>
|
#include <soc/pei_wrapper.h>
|
||||||
#include <soc/pm.h>
|
|
||||||
#include <soc/romstage.h>
|
#include <soc/romstage.h>
|
||||||
#include "gpio.h"
|
#include "gpio.h"
|
||||||
#include "spd/spd.h"
|
#include "spd/spd.h"
|
||||||
@ -45,7 +44,6 @@ void mainboard_romstage_entry(struct romstage_params *params)
|
|||||||
/* Ensure the EC and PD are in the right mode for recovery */
|
/* Ensure the EC and PD are in the right mode for recovery */
|
||||||
google_chromeec_early_init();
|
google_chromeec_early_init();
|
||||||
|
|
||||||
post_code(0x31);
|
|
||||||
early_config_gpio();
|
early_config_gpio();
|
||||||
|
|
||||||
/* Fill out PEI DATA */
|
/* Fill out PEI DATA */
|
||||||
@ -55,23 +53,14 @@ void mainboard_romstage_entry(struct romstage_params *params)
|
|||||||
romstage_common(params);
|
romstage_common(params);
|
||||||
}
|
}
|
||||||
|
|
||||||
void mainboard_memory_init_params(
|
void mainboard_memory_init_params(struct romstage_params *params,
|
||||||
struct romstage_params *params,
|
MEMORY_INIT_UPD *memory_params)
|
||||||
MEMORY_INIT_UPD *memory_params)
|
|
||||||
{
|
{
|
||||||
if (params->pei_data->spd_data[0][0][0] != 0) {
|
if (params->pei_data->spd_data[0][0][0] != 0) {
|
||||||
memory_params->MemorySpdPtr00 =
|
memory_params->MemorySpdPtr00 =
|
||||||
(UINT32)(params->pei_data->spd_data[0][0]);
|
(UINT32)(params->pei_data->spd_data[0][0]);
|
||||||
memory_params->MemorySpdPtr10 =
|
memory_params->MemorySpdPtr10 =
|
||||||
(UINT32)(params->pei_data->spd_data[1][0]);
|
(UINT32)(params->pei_data->spd_data[1][0]);
|
||||||
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
|
|
||||||
memory_params->MemorySpdPtr00);
|
|
||||||
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n",
|
|
||||||
memory_params->MemorySpdPtr01);
|
|
||||||
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",
|
|
||||||
memory_params->MemorySpdPtr10);
|
|
||||||
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n",
|
|
||||||
memory_params->MemorySpdPtr11);
|
|
||||||
}
|
}
|
||||||
memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
|
memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
|
||||||
sizeof(params->pei_data->dq_map[0]));
|
sizeof(params->pei_data->dq_map[0]));
|
||||||
@ -88,3 +77,18 @@ void mainboard_memory_init_params(
|
|||||||
memory_params->MemorySpdDataLen = SPD_LEN;
|
memory_params->MemorySpdDataLen = SPD_LEN;
|
||||||
memory_params->DqPinsInterleaved = FALSE;
|
memory_params->DqPinsInterleaved = FALSE;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void mainboard_add_dimm_info(struct romstage_params *params,
|
||||||
|
struct memory_info *mem_info,
|
||||||
|
int channel, int dimm, int index)
|
||||||
|
{
|
||||||
|
/* Set the manufacturer */
|
||||||
|
memcpy(&mem_info->dimm[index].mod_id,
|
||||||
|
¶ms->pei_data->spd_data[channel][dimm][SPD_MANU_OFF],
|
||||||
|
sizeof(mem_info->dimm[index].mod_id));
|
||||||
|
|
||||||
|
/* Set the module part number */
|
||||||
|
memcpy(mem_info->dimm[index].module_part_number,
|
||||||
|
¶ms->pei_data->spd_data[channel][dimm][SPD_PART_OFF],
|
||||||
|
sizeof(mem_info->dimm[index].module_part_number));
|
||||||
|
}
|
||||||
|
@ -19,17 +19,18 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <arch/byteorder.h>
|
#include <arch/byteorder.h>
|
||||||
|
#include <boardid.h>
|
||||||
#include <cbfs.h>
|
#include <cbfs.h>
|
||||||
#include <console/console.h>
|
#include <console/console.h>
|
||||||
#include <string.h>
|
|
||||||
#include <gpio.h>
|
#include <gpio.h>
|
||||||
#include <soc/gpio.h>
|
#include <soc/gpio.h>
|
||||||
#include <soc/pei_data.h>
|
#include <soc/pei_data.h>
|
||||||
#include <soc/romstage.h>
|
#include <soc/romstage.h>
|
||||||
#include <ec/google/chromeec/ec.h>
|
#include <string.h>
|
||||||
#include <mainboard/intel/kunimitsu/spd/spd.h>
|
|
||||||
#include <boardid.h>
|
#include "../boardid.h"
|
||||||
#include <mainboard/intel/kunimitsu/boardid.h>
|
#include "../gpio.h"
|
||||||
|
#include "spd.h"
|
||||||
|
|
||||||
static void mainboard_print_spd_info(uint8_t spd[])
|
static void mainboard_print_spd_info(uint8_t spd[])
|
||||||
{
|
{
|
||||||
@ -90,10 +91,10 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
|
|||||||
int spd_index, sku_id;
|
int spd_index, sku_id;
|
||||||
|
|
||||||
gpio_t spd_gpios[] = {
|
gpio_t spd_gpios[] = {
|
||||||
GPP_C12, /* PCH_MEM_CONFIG[0] */
|
GPIO_MEM_CONFIG_0,
|
||||||
GPP_C13, /* PCH_MEM_CONFIG[1] */
|
GPIO_MEM_CONFIG_1,
|
||||||
GPP_C14, /* PCH_MEM_CONFIG[2] */
|
GPIO_MEM_CONFIG_2,
|
||||||
GPP_C15, /* PCH_MEM_CONFIG[3] */
|
GPIO_MEM_CONFIG_3,
|
||||||
};
|
};
|
||||||
|
|
||||||
spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||||
@ -102,8 +103,8 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
|
|||||||
* and not SKU ID but on SCRD it indicates SKU.
|
* and not SKU ID but on SCRD it indicates SKU.
|
||||||
*/
|
*/
|
||||||
sku_id = board_id();
|
sku_id = board_id();
|
||||||
printk(BIOS_ERR, "SPD index %d\n", spd_index);
|
printk(BIOS_INFO, "SPD index %d\n", spd_index);
|
||||||
printk(BIOS_ERR, "Board ID %d\n", sku_id);
|
printk(BIOS_INFO, "Board ID %d\n", sku_id);
|
||||||
|
|
||||||
/* Load SPD data from CBFS */
|
/* Load SPD data from CBFS */
|
||||||
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
|
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
|
||||||
|
@ -18,8 +18,8 @@
|
|||||||
* Foundation, Inc.
|
* Foundation, Inc.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef _MAINBOARD_SPD_H_
|
#ifndef MAINBOARD_SPD_H
|
||||||
#define _MAINBOARD_SPD_H_
|
#define MAINBOARD_SPD_H
|
||||||
|
|
||||||
#define SPD_LEN 256
|
#define SPD_LEN 256
|
||||||
|
|
||||||
@ -32,6 +32,6 @@
|
|||||||
#define SPD_BUS_DEV_WIDTH 8
|
#define SPD_BUS_DEV_WIDTH 8
|
||||||
#define SPD_PART_OFF 128
|
#define SPD_PART_OFF 128
|
||||||
#define SPD_PART_LEN 18
|
#define SPD_PART_LEN 18
|
||||||
|
#define SPD_MANU_OFF 148
|
||||||
|
|
||||||
|
#endif
|
||||||
#endif /* _MAINBOARD_SPD_H_ */
|
|
||||||
|
@ -1,36 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2013 Google Inc.
|
|
||||||
* Copyright (C) 2015 Intel Corporation.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _MAINBOARD_THERMAL_H_
|
|
||||||
#define _MAINBOARD_THERMAL_H_
|
|
||||||
|
|
||||||
#define TEMPERATURE_SENSOR_ID 0 /* PECI */
|
|
||||||
|
|
||||||
/* Temperature which OS will shutdown at */
|
|
||||||
#define CRITICAL_TEMPERATURE 104
|
|
||||||
|
|
||||||
/* Temperature which OS will throttle CPU */
|
|
||||||
#define PASSIVE_TEMPERATURE 95
|
|
||||||
|
|
||||||
/* Tj_max value for calculating PECI CPU temperature */
|
|
||||||
/* Tj_max can be read by MSR 0x1A2, BITS[23:16] */
|
|
||||||
#define MAX_TEMPERATURE 100
|
|
||||||
|
|
||||||
#endif /* _MAINBOARD_THERMAL_H_ */
|
|
Reference in New Issue
Block a user