arch to drivers/intel: Fix misspellings & capitalization issues

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/arm64/armv8/exception.c

@@ -160,7 +160,7 @@ void exc_dispatch(struct exc_state *state, uint64_t idx)
 
 static int test_exception_handler(struct exc_state *state, uint64_t vector_id)
 {
-	/* Update instruction pointer to next instrution. */
+	/* Update instruction pointer to next instruction. */
 	state->elx.elr += sizeof(uint32_t);
 	raw_write_elr_el3(state->elx.elr);
 	return EXC_RET_HANDLED;

src/arch/x86/exception.c

@@ -305,7 +305,7 @@ static int get_packet(char *buffer)
 	int count;
 	char ch;
 
-	/* Wishlit implement a timeout in get_packet */
+	/* TODO: implement a timeout in get_packet */
 	do {
 		/* wait around for the start character, ignore all other
 		 * characters

src/commonlib/bsd/lz4_wrapper.c

@@ -8,7 +8,7 @@
 
 /* LZ4 comes with its own supposedly portable memory access functions, but they
  * seem to be very inefficient in practice (at least on ARM64). Since coreboot
- * knows about endinaness and allows some basic assumptions (such as unaligned
+ * knows about endianness and allows some basic assumptions (such as unaligned
  * access support), we can easily write the ones we need ourselves. */
 static uint16_t LZ4_readLE16(const void *src)
 {

src/commonlib/include/commonlib/coreboot_tables.h

@@ -528,7 +528,7 @@ struct	cmos_checksum {
 struct lb_smmstorev2 {
 	uint32_t tag;
 	uint32_t size;
-	uint32_t num_blocks;		/* Number of writeable blocks in SMM */
+	uint32_t num_blocks;		/* Number of writable blocks in SMM */
 	uint32_t block_size;		/* Size of a block in byte. Default: 64 KiB */
 	uint32_t mmap_addr;		/* MMIO address of the store for read only access */
 	uint32_t com_buffer;		/* Physical address of the communication buffer */

src/commonlib/include/commonlib/loglevel.h

@@ -182,7 +182,7 @@ static const char bios_log_prefix[BIOS_LOG_PREFIX_MAX_LEVEL + 1][5] = {
  * When printing to terminals supporting ANSI escape sequences, the following
  * escape sequences can be printed to highlight the respective log levels
  * according to the BIOS_LOG_ESCAPE_PATTERN printf() pattern. At the end of a
- * line, highlighting should be reset with the BIOS_LOG_ESCAPE_RESET seqence.
+ * line, highlighting should be reset with the BIOS_LOG_ESCAPE_RESET sequence.
  *
  * The escape sequences used here set flags with the following meanings:
  * 1 = bold, 4 = underlined, 5 = blinking, 7 = inverted

src/commonlib/include/commonlib/timestamp_serialized.h

@@ -295,7 +295,7 @@ static const struct timestamp_id_to_name {
 
 	/* Intel ME related timestamps */
 	TS_NAME_DEF(TS_ME_INFORM_DRAM_START, TS_ME_INFORM_DRAM_END,
-		    "waiting for ME acknowledgement of raminit"),
+		    "waiting for ME acknowledgment of raminit"),
 	TS_NAME_DEF(TS_ME_INFORM_DRAM_END, 0, "finished waiting for ME response"),
 	TS_NAME_DEF(TS_ME_END_OF_POST_START, TS_ME_END_OF_POST_END, "before sending EOP to ME"),
 	TS_NAME_DEF(TS_ME_END_OF_POST_END, 0, "after sending EOP to ME"),

src/cpu/x86/lapic/apic_timer.c

@@ -33,7 +33,7 @@ void udelay(u32 usecs)
 		timer_fsb = get_timer_fsb();
 	}
 
-	/* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz
+	/* Calculate the number of ticks to run, our FSB runs at timer_fsb MHz
 	 */
 	ticks = usecs * timer_fsb;
 	start = lapic_read(LAPIC_TMCCT);

src/cpu/x86/mp_init.c

@@ -777,7 +777,7 @@ static enum cb_err install_permanent_handler(int num_cpus, uintptr_t smbase,
 				     size_t smsize, size_t save_state_size)
 {
 	/*
-	 * All the CPUs will relocate to permanaent handler now. Set parameters
+	 * All the CPUs will relocate to permanent handler now. Set parameters
 	 * needed for all CPUs. The placement of each CPUs entry point is
 	 * determined by the loader. This code simply provides the beginning of
 	 * SMRAM region, the number of CPUs who will use the handler, the stack

src/device/device.c

@@ -579,7 +579,7 @@ void dev_initialize(void)
  * Finalize a specific device.
  *
  * The parent should be finalized first to avoid having an ordering problem.
- * This is done by calling the parent's final() method before its childrens'
+ * This is done by calling the parent's final() method before its children's
  * final() methods.
  *
  * @param dev The device to be initialized.

src/device/oprom/yabel/debug.h

@@ -70,7 +70,7 @@ static inline void set_ci(void) {};
  * |||||||||-DEBUG_VBE - Print messages related to VESA BIOS Extension (VBE) functions
  * ||||||||||-DEBUG_PRINT_INT10 - let INT10 (i.e. character output) calls print messages to Debug output
  * |||||||||||-DEBUG_INTR - Print messages related to interrupt handling
- * ||||||||||||-DEBUG_CHECK_VMEM_ACCESS - Print messages related to accesse to certain areas of the virtual Memory (e.g. BDA (BIOS Data Area) or Interrupt Vectors)
+ * ||||||||||||-DEBUG_CHECK_VMEM_ACCESS - Print messages related to accesses to certain areas of the virtual Memory (e.g. BDA (BIOS Data Area) or Interrupt Vectors)
  * |||||||||||||-DEBUG_MEM - Print memory access made by option ROM (NOTE: this also includes accesses to fetch instructions)
  * ||||||||||||||-DEBUG_IO - Print I/O access made by option rom
  * 11000111111111 - Max Binary Value, Debug All (WARNING: - This could run for hours)

src/device/pci_class.c

@@ -93,7 +93,7 @@ static const PCI_SUBCLASS communication[] = {
 	{ 0x02, "Multiport serial controller" },
 	{ 0x03, "Modem" },
 	{ 0x04, "GPIB controller" },
-	{ 0x05, "Smard Card controller" },
+	{ 0x05, "Smart Card controller" },
 	{ 0x80, "Communication controller" }
 };
 

src/drivers/analogix/anx7625/anx7625.h

@@ -189,7 +189,7 @@
 #define AP_AV_STATUS 0x28
 #define AP_VIDEO_CHG (1<<2)
 #define AP_AUDIO_CHG (1<<3)
-#define AP_MIPI_MUTE (1<<4) /* 1:MIPI input mute, 0: ummute */
+#define AP_MIPI_MUTE (1<<4) /* 1:MIPI input mute, 0: unmute */
 #define AP_MIPI_RX_EN (1<<5) /* 1: MIPI RX input in  0: no RX in */
 #define AP_DISABLE_PD (1<<6)
 #define AP_DISABLE_DISPLAY (1<<7)

src/drivers/aspeed/common/ast_main.c

@@ -440,7 +440,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
 		if (ret)
 			goto out_free;
 		ast->vram_size = ast_get_vram_info(dev);
-		DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
+		DRM_INFO("dram MCLK=%u MHz type=%d bus_width=%d size=%08x\n",
 			 ast->mclk, ast->dram_type,
 			 ast->dram_bus_width, ast->vram_size);
 	}

src/drivers/i2c/rtd2132/chip.h

@@ -11,7 +11,7 @@ struct drivers_i2c_rtd2132_config {
 	u16 t4; /* Delay from backlight output disable to PWM output disable. */
 	u16 t5; /* Delay from PWM output disable to LVDS output disable. */
 	u16 t6; /* Delay from LVDS output disable to panel Vcc disable. */
-	u16 t7; /* Delay between tweo panel power on/off sequence. */
+	u16 t7; /* Delay between two panel power on/off sequence. */
 
 	/*
 	 * LVDS swap.

src/drivers/i2c/tpm/cr50.c

@@ -123,7 +123,7 @@ static int cr50_i2c_write(uint8_t addr, const uint8_t *buffer, size_t len)
 }
 
 /*
- * Cr50 processes reset requests asynchronously and consceivably could be busy
+ * Cr50 processes reset requests asynchronously and conceivably could be busy
  * executing a long command and not reacting to the reset pulse for a while.
  *
  * This function will make sure that the AP does not proceed with boot until

src/drivers/i2c/ww_ring/ww_ring.c

@@ -310,7 +310,7 @@ static int ledc_init_validate(TiLp55231 *ledc)
 	}
 
 	/*
-	 * Signal Depthcharge that the controller has been initiazed by
+	 * Signal Depthcharge that the controller has been initialized by
 	 * coreboot.
 	 */
 	data = LP55231_VARIABLE_COOKIE;
@@ -340,7 +340,7 @@ int ww_ring_display_pattern(unsigned int i2c_bus, enum display_pattern pattern)
 
 			/*
 			 * First stop all running programs to avoid
-			 * inerference between the controllers.
+			 * interference between the controllers.
 			 */
 			for (j = 0; j < WW_RING_NUM_LED_CONTROLLERS; j++) {
 				if (!lp55231s[j].dev_addr)

src/drivers/i2c/ww_ring/ww_ring.h

@@ -5,12 +5,12 @@
 
 /*
  * Different types of display patterns to be shown by the LED ring while
- * contrlled by coreboot.
+ * controlled by coreboot.
  */
 enum display_pattern {
 	WWR_ALL_OFF,		/* Turn the LEDs off. */
 	WWR_RECOVERY_PUSHED,	/* Recovery button push detected on start up. */
-	WWR_WIPEOUT_REQUEST,	/* Held long enough for wipout request. */
+	WWR_WIPEOUT_REQUEST,	/* Held long enough for wipeout request. */
 	WWR_RECOVERY_REQUEST,	/* Held long enough for recovery request. */
 	WWR_NORMAL_BOOT		/* No buttons pressed, normal boot sequence. */
 };

src/drivers/i2c/ww_ring/ww_ring_programs.c

@@ -89,7 +89,7 @@ static const TiLp55231Program solid_000000_program = {
  * The three internal engines seem to be competing for resources and get out
  * of sync in seconds if left running asynchronously.
  *
- * When solid patterns are deployed with instanteneous color intensity
+ * When solid patterns are deployed with instantaneous color intensity
  * changes, all three LEDs can be controlled by one engine in sequential
  * accesses. But the controllers still need to be synchronized.
  *

src/drivers/intel/dptf/dptf.c

@@ -537,7 +537,7 @@ static void write_device_definitions(const struct device *dev)
 	acpigen_pop_len(); /* Scope */
 }
 
-/* Emites policy definitions for each policy type */
+/* Emits policy definitions for each policy type */
 static void write_policies(const struct drivers_intel_dptf_config *config)
 {
 	dptf_write_enabled_policies(config->policies.active, DPTF_MAX_ACTIVE_POLICIES,

src/drivers/intel/fsp1_1/include/fsp/util.h

@@ -29,7 +29,7 @@ void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
 	uint64_t new);
 void report_fsp_output(void);
 
-/* Return version of FSP associated with fih. */
+/* Return version of FSP associated with FIH. */
 static inline uint32_t fsp_version(FSP_INFO_HEADER *fih)
 {
 	return fih->ImageRevision;

src/drivers/intel/fsp1_1/raminit.c

@@ -239,7 +239,7 @@ void raminit(struct romstage_params *params)
 	mrc_hob = get_guid_hob(&mrc_guid, hob_list_ptr);
 	if (mrc_hob == NULL) {
 		printk(BIOS_DEBUG,
-			"Memory Configuration Data Hob not present\n");
+			"Memory Configuration Data HOB not present\n");
 	} else {
 		params->data_to_save = GET_GUID_HOB_DATA(mrc_hob);
 		params->data_to_save_size = ALIGN_UP(

src/drivers/intel/fsp1_1/romstage.c

@@ -85,7 +85,7 @@ static void raminit_common(struct romstage_params *params)
 	if (!s3wake)
 		mainboard_save_dimm_info(params);
 
-	/* Create romstage handof information */
+	/* Create romstage handoff information */
 	if (romstage_handoff_init(
 			params->power_state->prev_sleep_state == ACPI_S3) < 0)
 		/* FIXME: A "system" reset is likely enough: */

src/drivers/intel/fsp2_0/fsp_gop_blt.c

@@ -207,7 +207,7 @@ static void *fill_blt_buffer(efi_bmp_image_header *header,
 				gop_blt->Red   = *bmp_image;
 				break;
 
-			/* Conver 32 bit to 24bit bmp - just ignore the final byte of each pixel */
+			/* Convert 32 bit to 24bit bmp - just ignore the final byte of each pixel */
 			case 32:
 				gop_blt->Blue  = *bmp_image++;
 				gop_blt->Green = *bmp_image++;

src/drivers/intel/fsp2_0/fsp_timestamp.c

@@ -32,7 +32,7 @@ struct generic_event_record {
 } __packed;
 
 /*
- * Performance Hob:
+ * Performance HOB:
  *   GUID - fpdt_guid;
  *   Data - FPDT_PEI_EXT_PERF_HEADER one or more FPDT records
 */

src/drivers/intel/fsp2_0/hand_off_block.c

@@ -107,10 +107,10 @@ static void save_hob_list(int is_recovery)
 	const void *hob_list;
 	cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*cbmem_loc));
 	if (cbmem_loc == NULL)
-		die("Error: Could not add cbmem area for hob list.\n");
+		die("Error: Could not add cbmem area for HOB list.\n");
 	hob_list = fsp_get_hob_list();
 	if (!hob_list)
-		die("Error: Could not locate hob list pointer.\n");
+		die("Error: Could not locate HOB list pointer.\n");
 	*cbmem_loc = (uintptr_t)hob_list;
 }
 

src/drivers/intel/fsp2_0/hob_display.c

@@ -123,7 +123,7 @@ const char *fsp_get_hob_type_name(const struct hob_header *hob)
 		if (hob->type == hob_type_names[index].type)
 			return hob_type_names[index].name;
 
-	/* Get name for SOC specific hob */
+	/* Get name for SOC specific HOB */
 	name = soc_get_hob_type_name(hob);
 	if (name != NULL)
 		return name;
@@ -162,7 +162,7 @@ void fsp_print_guid_extension_hob(const struct hob_header *hob)
 	fsp_print_guid(BIOS_SPEW, res->owner_guid);
 	printk(BIOS_SPEW, ": %s\n", fsp_get_guid_name(res->owner_guid));
 
-	/* Some of the SoC FSP specific hobs are of type HOB_TYPE_GUID_EXTENSION */
+	/* Some of the SoC FSP specific HOBs are of type HOB_TYPE_GUID_EXTENSION */
 	soc_display_hob(hob);
 }
 

src/drivers/intel/fsp2_0/include/fsp/util.h

@@ -123,7 +123,7 @@ enum cb_err fsp_hob_iterator_get_next_guid_extension(const struct hob_header **h
 						     const uint8_t guid[16],
 						     const void **data, size_t *size);
 
-/* Function to extract the FSP timestamp from FPDT Hob and display */
+/* Function to extract the FSP timestamp from FPDT HOB and display */
 void fsp_display_timestamp(void);
 const void *fsp_get_hob_list(void);
 void *fsp_get_hob_list_ptr(void);

src/drivers/intel/fsp2_0/memory_init.c

@@ -80,7 +80,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t version)
 			save_memory_training_data();
 	}
 
-	/* Create romstage handof information */
+	/* Create romstage handoff information */
 	romstage_handoff_init(s3wake);
 }
 

src/drivers/intel/gma/i915_reg.h

@@ -15,7 +15,7 @@
  * The Bridge device's PCI config space has information about the
  * fb aperture size and the amount of pre-reserved memory.
  * This is all handled in the intel-gtt.ko module. i915.ko only
- * cares about the vga bit for the vga rbiter.
+ * cares about the vga bit for the vga arbiter.
  */
 #define INTEL_GMCH_CTRL		0x52
 #define INTEL_GMCH_VGA_DISABLE  (1 << 1)
@@ -1384,7 +1384,7 @@
 #define   SDVOC_GANG_MODE		(1 << 16)
 #define   SDVO_ENCODING_SDVO		(0x0 << 10)
 #define   SDVO_ENCODING_HDMI		(0x2 << 10)
-/** Requird for HDMI operation */
+/** Required for HDMI operation */
 #define   SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
 #define   SDVO_COLOR_RANGE_16_235	(1 << 8)
 #define   SDVO_BORDER_ENABLE		(1 << 7)
@@ -1485,7 +1485,7 @@
 
 /* Video Data Island Packet control */
 #define VIDEO_DIP_DATA		0x61178
-/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
+/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
  * of the infoframe structure specified by CEA-861. */
 #define   VIDEO_DIP_DATA_SIZE	32
@@ -1630,7 +1630,7 @@
 #define BLC_HIST_CTL		0x61260
 
 /* New registers for PCH-split platforms. Safe where new bits show up, the
- * register layout machtes with gen4 BLC_PWM_CTL[12]. */
+ * register layout matches with gen4 BLC_PWM_CTL[12]. */
 #define BLC_PWM_CPU_CTL2	0x48250
 #define  BLC_PWM2_ENABLE        (1UL<<31)
 #define BLC_PWM_CPU_CTL		0x48254
@@ -2037,7 +2037,7 @@
 /** Sets the rollover for the second subcarrier phase generation DDA */
 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
 # define TV_SCDDA2_SIZE_SHIFT		16
-/** Sets the increent of the second subcarrier phase generation DDA */
+/** Sets the increment of the second subcarrier phase generation DDA */
 # define TV_SCDDA2_INC_MASK		0x00007fff
 # define TV_SCDDA2_INC_SHIFT		0
 
@@ -2045,7 +2045,7 @@
 /** Sets the rollover for the third subcarrier phase generation DDA */
 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
 # define TV_SCDDA3_SIZE_SHIFT		16
-/** Sets the increent of the third subcarrier phase generation DDA */
+/** Sets the increment of the third subcarrier phase generation DDA */
 # define TV_SCDDA3_INC_MASK		0x00007fff
 # define TV_SCDDA3_INC_SHIFT		0
 

src/drivers/intel/gma/opregion.h

@@ -127,7 +127,7 @@ typedef struct {
 	u32	aslc;		/* Offset 4   ASLE interrupt command / status */
 	u32	tche;		/* Offset 8   Technology enabled indicator */
 	u32	alsi;		/* Offset 12  Current ALS illuminance reading */
-	u32	bclp;		/* Offset 16  Backlight britness to set */
+	u32	bclp;		/* Offset 16  Backlight brightness to set */
 	u32	pfit;		/* Offset 20  Panel fitting Request */
 	u32	cblv;		/* Offset 24  Brightness Current State */
 	u16	bclm[20];	/* Offset 28  Backlight Brightness Level Duty

src/drivers/intel/mipi_camera/chip.h

@@ -112,7 +112,7 @@ struct resource_config {
 struct clk_config {
 	/* IMGCLKOUT_x being used for a port */
 	uint8_t clknum;
-	/* frequency setting: 0:24Mhz, 1:19.2 Mhz */
+	/* frequency setting: 0:24MHz, 1:19.2 MHz */
 	uint8_t freq;
 };