cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE

CPU's featuring a non eviction mode cache the whole ROM.
Therefore XIP stages don't need to follow some alignment constraints.

Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/cpu/intel/model_2065x/Kconfig

@@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
 	select CPU_INTEL_COMMON
+	select NO_FIXED_XIP_ROM_SIZE
 
 config BOOTBLOCK_CPU_INIT
 	string
@@ -28,8 +29,4 @@ config SMM_TSEG_SIZE
 	hex
 	default 0x800000
 
-config XIP_ROM_SIZE
-	hex
-	default 0x20000
-
 endif