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Peppy/Haswell: move more support functions from mainboard to the intel i915 driver

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Move (and rename to make it clearer) the function that computes display
parameters from the dpcd and edid.

Change-Id: Idfbb56fd312b23c742c52abca1a34ae117a8fece
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171366
Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit 8f2b3bafee7cb05db8fae1c52fc9e1ee64e5e35d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6768
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Ronald G. Minnich
2013-10-01 10:46:35 -07:00
committed by Isaac Christensen
parent d7c25b357f
commit 74fade43ee
6 changed files with 140 additions and 119 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/drivers/intel/gma/Makefile.inc
View File

@ -17,6 +17,6 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c display.c
ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c
ramstage-$(CONFIG_INTEL_EDID) += edid.c ramstage-$(CONFIG_INTEL_EDID) += edid.c

118
src/drivers/intel/gma/display.c Normal file
View File

@ -0,0 +1,118 @@
/*
* Copyright 2013 Google Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Keith Packard <keithp@keithp.com>
*
*/
/* This code was created by the coccinnelle filters in the i915tool,
* with some final hand filtering.
*/
#include <console/console.h>
#include <stdint.h>
#include <delay.h>
#include <drivers/intel/gma/i915.h>
#include <string.h>
void compute_display_params(struct intel_dp *dp)
{
struct edid *edid = &(dp->edid);
/* step 1: get the constants in the dp struct set up. */
dp->lane_count = dp->dpcd[DP_MAX_LANE_COUNT]&DP_LANE_COUNT_MASK;
dp->link_bw = dp->dpcd[DP_MAX_LINK_RATE];
dp->clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
/* step 2. Do some computation of other stuff. */
dp->bytes_per_pixel = dp->pipe_bits_per_pixel/8;
dp->stride = edid->bytes_per_line;
dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
dp->hsync = (edid->ha + edid->hso - 1) |
((edid->ha + edid->hso + edid->hspw - 1) << 16);
dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
dp->vsync = (edid->va + edid->vso - 1) |
((edid->va + edid->vso + edid->vspw - 1) << 16);
/* PIPEASRC is wid-1 x ht-1 */
dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
dp->pfa_pos = 0;
dp->pfa_ctl = PF_ENABLE | PF_FILTER_MED_3x3;
/* IVB hack */
if (dp->gen == 6)
dp->pfa_ctl |= PF_PIPE_SEL_IVB(dp->pipe);
dp->pfa_sz = (edid->ha << 16) | (edid->va);
/* step 3. Call the linux code we pulled in. */
dp->flags = intel_ddi_calc_transcoder_flags(edid->panel_bits_per_pixel,
dp->port,
dp->pipe,
dp->type,
dp->lane_count,
dp->pfa_sz,
dp->edid.phsync == '+'?1:0,
dp->edid.pvsync == '+'?1:0);
dp->transcoder = intel_ddi_get_transcoder(dp->port,
dp->pipe);
intel_dp_compute_m_n(edid->panel_bits_per_pixel,
dp->lane_count,
dp->edid.pixel_clock,
dp->edid.link_clock,
&dp->m_n);
printk(BIOS_SPEW, "dp->lane_count = 0x%08x\n",dp->lane_count);
printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
printk(BIOS_SPEW, "0x6f030 = 0x%08x\n",
TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
}

4
src/drivers/intel/gma/i915.h
View File

@ -242,6 +242,7 @@ enum transcoder intel_ddi_get_transcoder(enum port port,
enum pipe pipe); enum pipe pipe);
void intel_dp_set_m_n_regs(struct intel_dp *intel_dp); void intel_dp_set_m_n_regs(struct intel_dp *intel_dp);
int intel_dp_bw_code_to_link_rate(u8 link_bw);
void intel_dp_set_resolution(struct intel_dp *intel_dp); void intel_dp_set_resolution(struct intel_dp *intel_dp);
int intel_dp_i2c_write(struct intel_dp *intel_dp, int intel_dp_i2c_write(struct intel_dp *intel_dp,
@ -278,3 +279,6 @@ u32 gtt_read(u32 reg);
int i915lightup(unsigned int physbase, unsigned int mmio, int i915lightup(unsigned int physbase, unsigned int mmio,
unsigned int gfx, unsigned int init_fb); unsigned int gfx, unsigned int init_fb);
/* display.c */
void compute_display_params(struct intel_dp *dp);

16
src/drivers/intel/gma/intel_dp.c
View File

@ -1787,6 +1787,22 @@ void intel_dp_set_m_n_regs(struct intel_dp *dp)
gtt_write(PIPE_LINK_N1(dp->transcoder),dp->m_n.link_n); gtt_write(PIPE_LINK_N1(dp->transcoder),dp->m_n.link_n);
} }
int intel_dp_bw_code_to_link_rate(u8 link_bw)
{
switch (link_bw) {
default:
printk(BIOS_ERR,
"ERROR: link_bw(%d) is bogus; must be one of 6, 0xa, or 0x14\n",
link_bw);
case DP_LINK_BW_1_62:
return 162000;
case DP_LINK_BW_2_7:
return 270000;
case DP_LINK_BW_5_4:
return 540000;
}
}
void intel_dp_set_resolution(struct intel_dp *intel_dp) void intel_dp_set_resolution(struct intel_dp *intel_dp)
{ {
gtt_write(HTOTAL(intel_dp->transcoder),intel_dp->htotal); gtt_write(HTOTAL(intel_dp->transcoder),intel_dp->htotal);

104
src/mainboard/google/peppy/gma.c
View File

@ -91,8 +91,6 @@ static unsigned int *mmio;
static unsigned int graphics; static unsigned int graphics;
static unsigned int physbase; static unsigned int physbase;
int intel_dp_bw_code_to_link_rate(u8 link_bw);
static int i915_init_done = 0; static int i915_init_done = 0;
/* fill the palette. */ /* fill the palette. */
@ -106,106 +104,6 @@ static void palette(void)
} }
} }
/* assumption: the dpcd in the dp is valid. The raw edid has been read
* and the translation has been done.
*/
void dp_init_dim_regs(struct intel_dp *dp);
void dp_init_dim_regs(struct intel_dp *dp)
{
struct edid *edid = &(dp->edid);
/* step 1: get the constants in the dp struct set up. */
dp->lane_count = dp->dpcd[DP_MAX_LANE_COUNT]&DP_LANE_COUNT_MASK;
dp->link_bw = dp->dpcd[DP_MAX_LINK_RATE];
dp->clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
/* step 2. Do some computation of other stuff. */
dp->bytes_per_pixel = dp->pipe_bits_per_pixel/8;
dp->stride = edid->bytes_per_line;
dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
dp->hsync = (edid->ha + edid->hso - 1) |
((edid->ha + edid->hso + edid->hspw - 1) << 16);
dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
dp->vsync = (edid->va + edid->vso - 1) |
((edid->va + edid->vso + edid->vspw - 1) << 16);
/* PIPEASRC is wid-1 x ht-1 */
dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
dp->pfa_pos = 0;
/* XXXXXXXXXXXXXX hard code */
dp->pfa_ctl = 0x80800000;
dp->pfa_sz = (edid->ha << 16) | (edid->va);
/* step 3. Call the linux code we pulled in. */
dp->flags = intel_ddi_calc_transcoder_flags(edid->panel_bits_per_pixel,
dp->port,
dp->pipe,
dp->type,
dp->lane_count,
dp->pfa_sz,
dp->edid.phsync == '+'?1:0,
dp->edid.pvsync == '+'?1:0);
dp->transcoder = intel_ddi_get_transcoder(dp->port,
dp->pipe);
intel_dp_compute_m_n(edid->panel_bits_per_pixel,
dp->lane_count,
dp->edid.pixel_clock,
dp->edid.link_clock,
&dp->m_n);
printk(BIOS_SPEW, "dp->lane_count = 0x%08x\n",dp->lane_count);
printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
printk(BIOS_SPEW, "0x6f030 = 0x%08x\n",
TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
}
int intel_dp_bw_code_to_link_rate(u8 link_bw)
{
switch (link_bw) {
default:
printk(BIOS_ERR,
"ERROR: link_bw(%d) is bogus; must be one of 6, 0xa, or 0x14\n",
link_bw);
case DP_LINK_BW_1_62:
return 162000;
case DP_LINK_BW_2_7:
return 270000;
case DP_LINK_BW_5_4:
return 540000;
}
}
void mainboard_train_link(struct intel_dp *intel_dp) void mainboard_train_link(struct intel_dp *intel_dp)
{ {
u8 read_val; u8 read_val;
@ -366,7 +264,7 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
dp_init_dim_regs(dp); compute_display_params(dp);
printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n", printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",
dp->edid.pixel_clock, dp->edid.link_clock); dp->edid.pixel_clock, dp->edid.link_clock);

15
src/mainboard/google/slippy/gma.c
View File

@ -214,21 +214,6 @@ void dp_init_dim_regs(struct intel_dp *dp)
printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags); printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
} }
int intel_dp_bw_code_to_link_rate(u8 link_bw);
int intel_dp_bw_code_to_link_rate(u8 link_bw)
{
switch (link_bw) {
case DP_LINK_BW_1_62:
default:
return 162000;
case DP_LINK_BW_2_7:
return 270000;
case DP_LINK_BW_5_4:
return 540000;
}
}
void mainboard_train_link(struct intel_dp *intel_dp) void mainboard_train_link(struct intel_dp *intel_dp)
{ {
u8 read_val; u8 read_val;