uart/sifive: make divisor configurable

The SiFive UART on the HiFive Unleashed uses the tlclk as input clock
which runs at coreclk / 2.

The input frequency is configured in the board code depending on the
current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz)

Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

src/soc/sifive/fu540/Kconfig

@@ -20,7 +20,7 @@ config SOC_SIFIVE_FU540
 	select ARCH_RAMSTAGE_RISCV
 	select BOOTBLOCK_CONSOLE
 	select DRIVERS_UART_SIFIVE
-
+	select UART_OVERRIDE_REFCLK
 if SOC_SIFIVE_FU540
 
 config RISCV_ARCH

src/soc/sifive/fu540/uart.c

@@ -23,3 +23,11 @@ uintptr_t uart_platform_base(int idx)
 	else
 		return 0;
 }
+
+unsigned int uart_platform_refclk(void)
+{
+	/*
+	 * The SiFive UART uses tlclk, which is coreclk/2 as input
+	 */
+	return 33330000 / 2;
+}