mb/google/brask/var/kuldax: Update overridetree
Update override devicetree based on schematics. BUG=b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
This commit is contained in:
David Wu
Felix Held
parent
e77cd0ec71
commit
7524c8dae5
@ -1,6 +1,248 @@
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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register "serial_io_gspi_mode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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}"
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device domain 0 on
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device domain 0 on
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end
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DRAM""
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register "options.tsr[1].desc" = ""Charger""
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# TODO: below values are initial reference values only
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## Active Policy
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(85, 90),
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TEMP_PCT(80, 80),
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TEMP_PCT(75, 70),
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}
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}
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}"
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
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[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 15000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 55000,
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.max_power = 55000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 6700, 220, 2200, },
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[1] = { 80, 5800, 180, 1800, },
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[2] = { 70, 5000, 145, 1450, },
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[3] = { 60, 4900, 115, 1150, },
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[4] = { 50, 3838, 90, 900, },
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[5] = { 40, 2904, 55, 550, },
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[6] = { 30, 2337, 30, 300, },
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[7] = { 20, 1608, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 alias dptf_policy on end
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end
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end
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device ref pcie4_0 on
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# Enable CPU PCIE RP 1 using CLK 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
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use tcss_usb3_port1 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c0 on
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chip drivers/i2c/nau8825
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register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
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register "jkdet_enable" = "1"
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register "jkdet_pull_enable" = "0"
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register "jkdet_pull_up" = "0"
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register "jkdet_polarity" = "1" # ActiveLow
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register "vref_impedance" = "2" # 125kOhm
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register "micbias_voltage" = "6" # 2.754
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register "sar_threshold_num" = "4"
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register "sar_threshold[0]" = "0x0C"
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register "sar_threshold[1]" = "0x1C"
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register "sar_threshold[2]" = "0x38"
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register "sar_threshold[3]" = "0x60"
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register "sar_hysteresis" = "1"
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register "sar_voltage" = "6"
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register "sar_compare_time" = "0" # 500ns
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register "sar_sampling_time" = "0" # 2us
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register "short_key_debounce" = "2" # 100ms
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register "jack_insert_debounce" = "7" # 512ms
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register "jack_eject_debounce" = "7" # 512ms
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device i2c 1a on end
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end
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end
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device ref pcie_rp7 on
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chip drivers/net
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register "wake" = "GPE0_DW0_07"
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register "led_feature" = "0xe0"
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register "customized_led0" = "0x23f"
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register "customized_led2" = "0x028"
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register "enable_aspm_l1_2" = "1"
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device pci 00.0 on end
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end
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end # RTL8125 Ethernet NIC
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device ref pcie_rp8 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
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register "srcclk_pin" = "3"
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device generic 0 on end
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end
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end #PCIE8 SD card
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device ref gspi1 off end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 0 alias conn0 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref tcss_usb3_port1 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A3 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(5, 1)"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A2 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(6, 1)"
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device ref usb2_port7 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A1 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(4, 1)"
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device ref usb2_port8 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device ref usb2_port9 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port10 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A1 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(4, 1)"
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device ref usb3_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A2 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(6, 1)"
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device ref usb3_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A3 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(5, 1)"
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device ref usb3_port4 on end
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end
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end
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end
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end
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end
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end
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end
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