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mb/lenovo/thinkcentre_m710s: Add SMBIOS data for PCIe slots

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Change-Id: Iaa761108acbf275820ecbec9837b81bc5d64613e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83991
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Nicholas Sudsgaard
2024-08-19 02:55:51 +00:00
committed by Felix Held
parent 81b417da06
commit 752962e553
1 changed files with 25 additions and 0 deletions
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25
src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
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@@ -5,6 +5,11 @@ chip soc/intel/skylake
device domain 0 on device domain 0 on
device ref peg0 on # PCIE16X device ref peg0 on # PCIE16X
smbios_slot_desc "SlotTypePciExpressGen3X16"
"SlotLengthLong"
"PCIE16X"
"SlotDataBusWidth16X"
# These configurations are technically for PCIe root # These configurations are technically for PCIe root
# ports. However, they are used as there is no # ports. However, they are used as there is no
# equivalent for PEG devices. # equivalent for PEG devices.
@@ -58,6 +63,11 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "true"
end end
device ref pcie_rp7 on # PCIE1X_2 device ref pcie_rp7 on # PCIE1X_2
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
"PCIE1X_2"
"SlotDataBusWidth1X"
register "PcieRpEnable[6]" = "true" register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "true"
register "PcieRpClkReqSupport[6]" = "true" register "PcieRpClkReqSupport[6]" = "true"
@@ -66,6 +76,11 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[6]" = "true" register "PcieRpAdvancedErrorReporting[6]" = "true"
end end
device ref pcie_rp8 on # PCIE1X_1 device ref pcie_rp8 on # PCIE1X_1
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
"PCIE1X_1"
"SlotDataBusWidth1X"
register "PcieRpEnable[7]" = "true" register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "true"
register "PcieRpClkReqSupport[7]" = "true" register "PcieRpClkReqSupport[7]" = "true"
@@ -74,6 +89,11 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[7]" = "true" register "PcieRpAdvancedErrorReporting[7]" = "true"
end end
device ref pcie_rp11 on # M2_WIFI device ref pcie_rp11 on # M2_WIFI
smbios_slot_desc "SlotTypeM2Socket1_SD"
"SlotLengthOther"
"M2_WIFI"
"SlotDataBusWidth1X"
register "PcieRpEnable[10]" = "true" register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "true"
register "PcieRpClkReqSupport[10]" = "true" register "PcieRpClkReqSupport[10]" = "true"
@@ -82,6 +102,11 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[10]" = "true" register "PcieRpAdvancedErrorReporting[10]" = "true"
end end
device ref pcie_rp21 on # M2_SSD device ref pcie_rp21 on # M2_SSD
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthOther"
"M2_SSD"
"SlotDataBusWidth1X"
register "PcieRpEnable[20]" = "true" register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "true"
register "PcieRpClkReqSupport[20]" = "true" register "PcieRpClkReqSupport[20]" = "true"