From 7542fa19a969dcd13a1fd23d23f91ad7898e5f65 Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Fri, 22 Sep 2023 00:38:53 +0530 Subject: [PATCH] soc/intel/mtl: Call cse_fill_bp_info early in romstage Intel Platform Service Record(PSR) will be enabled on Meteor Lake platforms. cse_fw_sync actions happen in ramstage when PSR is enabled. To avoid the boot time penalty of sending the cse_get_bp_info in ramstage, call cse_fill_bp_info to get cse_bp_info response early in romstage and store in cbmem. This data can be later used in ramstage. BUG=b:273207144 TEST=Verify cse_bp_info is filled in romstage in rex. Change-Id: Ic0e8fb34f21ff07e182a7b848d38e9d329010028 Signed-off-by: Krishna Prasad Bhat Signed-off-by: Rizwan Qureshi Reviewed-on: https://review.coreboot.org/c/coreboot/+/78056 Tested-by: build bot (Jenkins) Reviewed-by: Anil Kumar K Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal --- src/soc/intel/meteorlake/romstage/romstage.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index 3df480c3f5..1f1cfd6138 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -129,8 +129,11 @@ void mainboard_romstage_entry(void) /* Initialize HECI interface */ cse_init(HECI1_BASE_ADDRESS); - if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) - cse_fw_sync(); + if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + cse_fill_bp_info(); + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE)) + cse_fw_sync(); + } /* Update coreboot timestamp table with CSE timestamps */ if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))