soc/amd/common/fsp: add common CPPC data HOB support

Add common AMD FSP functionality to get the nominal and minimal CPU core
CPPC frequencies. Those functions will be used in the _CPC ACPI object
generation in a follow-up patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: I68ebdf610795d2673e0118a732f54f5f719b73c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66550
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/common/block/include/amdblocks/cppc.h

@@ -8,5 +8,7 @@
 
 struct cppc_config;
 void generate_cppc_entries(unsigned int core_id);
+enum cb_err get_ccx_cppc_min_frequency(uint32_t *freq);
+enum cb_err get_ccx_cppc_nom_frequency(uint32_t *freq);
 
 #endif /* AMD_CEZANNE_CPPC_H */

src/soc/amd/common/fsp/Kconfig

@@ -3,6 +3,9 @@ if PLATFORM_USES_FSP2_0
 config SOC_AMD_COMMON_FSP_DMI_TABLES
 	bool
 
+config SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
+	bool
+
 source "src/soc/amd/common/fsp/*/Kconfig"
 
 endif # PLATFORM_USES_FSP2_0

src/soc/amd/common/fsp/Makefile.inc

@@ -3,6 +3,7 @@ romstage-y += fsp_reset.c
 romstage-y += fsp_validate.c
 ramstage-y += fsp_reset.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_CCX_CPPC_HOB) += fsp_ccx_cppc_hob.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_FSP_DMI_TABLES) += dmi.c
 
 subdirs-y += ./*

src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c

@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/cppc.h>
+#include <ccx_cppc_data.h>
+#include <console/console.h>
+#include <FspGuids.h>
+#include <fsp/util.h>
+#include <string.h>
+#include <types.h>
+
+
+static enum cb_err get_ccx_cppc_data_hob(const struct fsp_ccx_cppc_data **cppc_data)
+{
+	static const struct fsp_ccx_cppc_data *cppc_data_cache;
+	size_t hob_size = 0;
+	const struct fsp_ccx_cppc_data *hob;
+
+	if (cppc_data_cache) {
+		*cppc_data = cppc_data_cache;
+		return CB_SUCCESS;
+	}
+
+	hob = fsp_find_extension_hob_by_guid(AMD_FSP_CCX_CPPC_DATA_HOB_GUID.b, &hob_size);
+
+	if (hob == NULL || hob_size < sizeof(struct fsp_ccx_cppc_data)) {
+		printk(BIOS_ERR, "Couldn't find CCX CPPC data HOB.\n");
+		return CB_ERR;
+	}
+
+	if (hob->version != FSP_CCX_CPPC_DATA_VERSION) {
+		printk(BIOS_ERR, "Unexpected CCX CPPC data HOB version.\n");
+		return CB_ERR;
+	}
+
+	cppc_data_cache = hob;
+	*cppc_data = cppc_data_cache;
+	return CB_SUCCESS;
+}
+
+enum cb_err get_ccx_cppc_min_frequency(uint32_t *freq)
+{
+	const struct fsp_ccx_cppc_data *cppc_data = NULL;
+
+	if (get_ccx_cppc_data_hob(&cppc_data) != CB_SUCCESS)
+		return CB_ERR;
+
+	*freq = cppc_data->ccx_cppc_min_speed;
+	printk(BIOS_SPEW, "CCX CPPC min speed: %d MHz\n", *freq);
+
+	return CB_SUCCESS;
+}
+
+enum cb_err get_ccx_cppc_nom_frequency(uint32_t *freq)
+{
+	const struct fsp_ccx_cppc_data *cppc_data = NULL;
+
+	if (get_ccx_cppc_data_hob(&cppc_data) != CB_SUCCESS)
+		return CB_ERR;
+
+	*freq = cppc_data->ccx_cppc_nom_speed;
+	printk(BIOS_SPEW, "CCX CPPC nom speed: %d MHz\n", *freq);
+
+	return CB_SUCCESS;
+}