mainboard/bap: Add support for BAP ODE E20XX

Adding new board based on AMD Kabini.
Most of the code is copied from gizmosphere/gizmo2
Board is developed by BAP - Bruhnspace Advanced Projects:
http://www.unibap.com/ (Site is under construction)
Special on this board is:
-Soldered down memory
-SuperIO Fintek F81866D
Known bugs:
-S3 doesnt work
-Serial ports only works for the first boot. Needs power cut.
Tested with:
-SeaBios as Payload
-Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1
-Windows 8 64Bit

Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10288
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/mainboard/bap/Kconfig

@@ -1,3 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+## (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
 if VENDOR_BAP
 
 choice

src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex

@@ -2,6 +2,8 @@
 # This file is part of the coreboot project.
 #
 # Copyright (C) 2014 Sage Electronic Engineering, LLC.
+# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+# (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -16,21 +18,17 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc. 
 
-# Gizmo2 has 1GB using 4 Micron_MT41J128M16JT-125 chips
+# BAP ODE E20XX has 2GB ram soldered down on the Q7
-# The datasheet is available at:
-# http://download.micron.com/pdf/datasheets/dram/ddr3/2Gb_DDR3_SDRAM.pdf
-
-#	SPD contents for Gizmo2 2GB DDR3 (1600MHz PC3-12800) soldered down
 
 #	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
 #		bits[3:0]: 1 = 128 SPD Bytes Used
 #		bits[6:4]: 1 = 256 SPD Bytes Total
 #		bit7     : 0 = CRC covers bytes 0 ~ 125
-11
+92
 
 #	1 SPD Revision -
 #		0x10 = Revision 1.0
-10
+12
 
 #	2 Key Byte / DRAM Device Type
 #		bits[7:0]: 0x0b = DDR3 SDRAM
@@ -45,13 +43,13 @@
 #		bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
 #		bits[6:4]: 0 = 3 (8 banks)
 #		bit7     :     reserved
-03
+04
 
 #	5 SDRAM Addressing
 #		bits[2:0]: 1 = 10 Column Address Bits
 #		bits[5:3]: 2 = 14 Row Address Bits
 #		bits[7:6]:     reserved
-11
+19
 
 #	6 Module Nominal Voltage, VDD
 #		bit0     : 0 = 1.5 V operable
@@ -70,7 +68,7 @@
 #		bits[2:0]: 3 = Primary bus width is 64 bits
 #		bits[4:3]: 0 = 0 bits (no bus width extension)
 #		bits[7:5]:     reserved
-03
+08
 
 #	9 Fine Timebase (FTB) Dividend / Divisor
 #		bits[3:0]: 0x02 divisor
@@ -85,7 +83,7 @@
 
 #	12 SDRAM Minimum Cycle Time (tCKmin)
 #		0x0a  = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
-0A
+0C
 
 #	13 Reserved
 00
@@ -93,11 +91,11 @@
 #	14 CAS Latencies Supported, Least Significant Byte
 #	15 CAS Latencies Supported, Most Significant Byte
 #		Cas Latencies of 11 - 5 are supported
-FE 00
+7E 00
 
 #	16 Minimum CAS Latency Time (tAAmin)
 #		0x6E = 13.75ns - DDR3-1600K
-6E
+69
 
 #	17 Minimum Write Recovery Time (tWRmin)
 #		0x78 = tWR of 15ns - All DDR3 speed grades
@@ -105,7 +103,7 @@ FE 00
 
 #	18 Minimum RAS# to CAS# Delay Time (tRCDmin)
 #		0x6E = 13.75ns -  DDR3-1600K
-6E
+69
 
 #	19 Minimum Row Active to Row Active Delay Time (tRRDmin)
 #		0x3C = 7.5ns
@@ -113,7 +111,7 @@ FE 00
 
 #	20 Minimum Row Precharge Delay Time (tRPmin)
 #		0x6E = 13.75ns -  DDR3-1600K
-6E
+69
 
 #	21 Upper Nibbles for tRAS and tRC
 #		bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
@@ -122,16 +120,16 @@ FE 00
 
 #	22 Minimum Active to Precharge Delay Time (tRASmin), LSB
 #		0x118 = 35ns - DDR3-1600 (see byte 21)
-18
+20
 
 #	23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
 #		0x186 = 48.75ns - DDR3-1600K
-86
+89
 
 #	24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
 #	25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
 #		0x500 = 160ns - for 2 Gigabit chips
-00 05
+20 08
 
 #	26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
 #		0x3c = 7.5 ns - All DDR3 SDRAM speed bins
@@ -144,7 +142,7 @@ FE 00
 #	28 Upper Nibble for tFAWmin
 #	29 Minimum Four Activate Window Delay Time (tFAWmin)
 #		0x0140 = 40ns -  DDR3-1600, 2 KB page size
-01 40
+01 68
 
 #	30 SDRAM Optional Feature
 #		bit0     : 1= RZQ/6 supported
@@ -160,7 +158,7 @@ FE 00
 #		bit3     : 0 = no on die thermal sensor
 #		bits[6:4]:     reserved
 #		bit7     : 0 = partial self refresh supported
-05
+01
 
 #	32 Module Thermal Sensor
 #		0 = Thermal sensor not incorporated onto this assembly
@@ -188,18 +186,18 @@ FE 00
 #	60 Raw Card Extension, Module Nominal Height
 #		bits[4:0]: 0 = <= 15mm tall
 #		bits[7:5]: 0 = raw card revision 0-3
-00
+0f
 
 #	61 Module Maximum Thickness
 #		bits[3:0]: 0 = thickness front <= 1mm
 #		bits[7:4]: 0 = thinkness back <= 1mm
-00
+11
 
 #	62 Reference Raw Card Used
 #		bits[4:0]: 0 = Reference Raw card A used
 #		bits[6:5]: 0 = revision 0
 #		bit7     : 0 = Reference raw cards A through AL
-00
+22
 
 #	63 Address Mapping from Edge Connector to DRAM
 #		bit0     : 0 = standard mapping (not mirrored)
@@ -217,19 +215,68 @@ FE 00
 
 #	117 - 118 Module ID: Module Manufacturers JEDEC ID Code
 #		0x0001 = AMD
-00 01
+80 AD
 
 #	119 Module ID: Module Manufacturing Location - oem specified
 #	120 Module ID: Module Manufacture Year in BCD
 #		0x13 = 2013
-00 13
+01 00
 
 #	121 Module ID: Module Manufacture week
 #		0x12 = 12th week
-12
+00
 
 #	122 - 125: Module Serial Number
-53 41 47 45
+00 00 00 00
 
 #	126 - 127: Cyclical Redundancy Code
-00 00
+D4 51
+
+# Coreboot is only interested in the first 128 values
+#128 - 135
+48 4d 54 34 32 35 53 36
+
+#136 - 143
+4d 46 52 36 43 2d 48 39
+
+#144 - 151
+20 20 4e 30 80 ad 00 00
+
+#152 - 159
+00 00 00 00 00 00 00 00
+
+#160 - 167
+00 00 00 00 00 00 00 00
+
+#168 - 175
+00 00 00 00 00 00 00 00
+
+#176 - 183
+00 00 00 00 00 00 00 00
+
+#184 - 191
+00 00 00 00 00 00 00 00
+
+#192 - 199
+00 00 00 00 00 00 00 00
+
+#200 - 207
+00 00 00 00 00 00 00 00
+
+#208 - 215
+00 00 00 00 00 00 00 00
+
+#216 - 223
+00 00 00 00 00 00 00 00
+
+#224 - 231
+00 00 00 00 00 00 00 00
+
+#232 - 239
+00 00 00 00 00 00 00 00
+
+#240 - 247
+00 00 00 00 00 00 00 00
+
+#248 - 255
+00 00 00 00 00 00 00 00

src/mainboard/bap/ode_e20XX/Kconfig

@@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_4096
 	select GFXUMA
+	select SUPERIO_FINTEK_F81866D
 	select SPD_CACHE
 
 config MAINBOARD_DIR

src/mainboard/bap/ode_e20XX/Makefile.inc

@@ -30,7 +30,7 @@ ramstage-y += PlatformGnbPcie.c
 SPD_BIN = $(obj)/spd.bin
 
 # Order of names in SPD_SOURCES is important!
-SPD_SOURCES  = Micron_MT41J128M16JT
+SPD_SOURCES  = BAP_Q7
 
 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
 

src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c

@@ -32,7 +32,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
 		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
-				HotplugDisabled,
+				HotplugBasic,
 				PcieGenMaxSupported,
 				PcieGenMaxSupported,
 				AspmDisabled, 0x01, 0)
@@ -42,7 +42,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
 		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
-				HotplugDisabled,
+				HotplugBasic,
 				PcieGenMaxSupported,
 				PcieGenMaxSupported,
 				AspmDisabled, 0x02, 0)
@@ -72,7 +72,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
 		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
-				HotplugDisabled,
+				HotplugBasic,
 				PcieGenMaxSupported,
 				PcieGenMaxSupported,
 				AspmDisabled, 0x05, 0)
@@ -80,17 +80,17 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
 };
 
 static const PCIe_DDI_DESCRIPTOR DdiList [] = {
-	/* DP0 to HDMI0/DP */
+	/* eDP0 to LVDS connector*/
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
+		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
 	},
-	/* DP1 to high-speed edge connector */
+	/* DP1 to HDMI */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
 		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
 	},
 };
 

src/mainboard/bap/ode_e20XX/acpi/superio.asl

@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+ * (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,4 +19,34 @@
  * Foundation, Inc.
  */
 
-/* No Super I/O device or functionality yet */
+/* SuperIO support for Windows */
+
+Device (UAR1) {
+	Name (_HID, EISAID ("PNP0501"))
+	Name (_UID, 1)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+		IRQNoFlags () {4}
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+		IRQNoFlags () {4}
+	})
+}
+
+Device (UAR2) {
+	Name (_HID, EISAID ("PNP0501"))
+	Name (_UID, 2)
+	Name (_CRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
+		IRQNoFlags () {3}
+	})
+	Name (_PRS, ResourceTemplate ()
+	{
+		IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08)
+		IRQNoFlags () {3}
+	})
+}

src/mainboard/bap/ode_e20XX/devicetree.cb

@@ -32,11 +32,11 @@ chip northbridge/amd/agesa/family16kb/root_complex
 				device pci 1.0 on  end # Internal Graphics P2P bridge 0x9835
 				device pci 1.1 on  end # Internal Multimedia
 				device pci 2.0 on  end # PCIe Host Bridge
-				device pci 2.1 on  end # PCIe GFX Bridge
+				device pci 2.1 on  end # x4 PCIe Slot
-				device pci 2.2 on  end # PCIe GPP mini PCIe
+				device pci 2.2 on  end # PCIe Q7 Realtek GBit LAN
-				device pci 2.3 on  end # PCIe LAN
+				device pci 2.3 on  end # PCIe CB Realtek GBit LAN
-				device pci 2.4 on  end # PCIe x2 to high speed edge connector
+				device pci 2.4 on  end # PCIe BAP FPGA
-				device pci 2.5 on  end # PCIe x2 to high speed edge connector
+				device pci 2.5 on  end # PCIe BAP FPGA (unused, for 050T)
 			end	#chip northbridge/amd/agesa/family16kb
 
 			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
@@ -48,7 +48,60 @@ chip northbridge/amd/agesa/family16kb/root_complex
 				device pci 13.2 on  end # USB
 				device pci 14.0 on  end # SM
 				device pci 14.2 on  end # HDA	0x4383
-				device pci 14.3 on  end # LPC	0x439d
+				device pci 14.3 on 	# LPC	0x439d
+					chip superio/fintek/f81866d
+						register "hwm_amd_tsi_addr" = "0x98"	# Set to AMD
+						register "hwm_amd_tsi_control" = "0x02"	# Set to AMD
+						register "hwm_fan_select" = "0xC0"	# Sets Fan2 to PWM
+						register "hwm_fan_mode" = "0xD5"	# Sets FAN1-3 to Auto RPM mode
+						register "hwm_fan3_control" = "0x00"	# Fan control 23kHz
+						register "hwm_fan2_temp_map_select" = "0x1E"	# Fan control 23kHz
+						register "hwm_fan2_bound1" = "0x3C"	# 60°C
+						register "hwm_fan2_bound2" = "0x32"	# 50°C
+						register "hwm_fan2_bound3" = "0x28"	# 40°C
+						register "hwm_fan2_bound4" = "0x1E"	# 30°C
+						register "hwm_fan2_seg1_speed" = "0xFF"	# 100%
+						register "hwm_fan2_seg2_speed" = "0xD9"	# 85%
+						register "hwm_fan2_seg3_speed" = "0xB2"	# 70%
+						register "hwm_fan2_seg4_speed" = "0x99"	# 60%
+						register "hwm_fan2_seg5_speed" = "0x80"	# 50%
+						register "hwm_temp_sens_type" = "0x04"	# Sets temp sensor 1 type to to thermistor
+						device pnp 4e.0 off		# Floppy
+							io 0x60 = 0x3f0
+							irq 0x70 = 6
+							drq 0x74 = 2
+						end
+						device pnp 4e.3 off end			# Parallel Port
+						device pnp 4e.4 on			# Hardware Monitor
+							io 0x60 = 0x295
+							irq 0x70 = 0
+						end
+						device pnp 4e.5 off #  Keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+						end
+						device pnp 4e.6 off end			# GPIO
+						device pnp 4e.7 on end			# WDT
+						device pnp 4e.a off end			# PME
+						device pnp 4e.10 on			# COM1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 4e.11 on			# COM2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 4e.12 off			# COM3
+						end
+						device pnp 4e.13 off			# COM4
+						end
+						device pnp 4e.14 off			# COM5
+						end
+						device pnp 4e.15 off			# COM6
+						end
+					end # f81866d
+				end #LPC
 				device pci 14.7 on  end # SD
 			end	#chip southbridge/amd/hudson
 

src/mainboard/bap/ode_e20XX/romstage.c

@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+ * (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -35,21 +37,16 @@
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 #include <cpu/amd/agesa/s3_resume.h>
+#include <superio/fintek/common/fintek.h>
+#include <superio/fintek/f81866d/f81866d.h>
 #include "cbmem.h"
 
+#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
-	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
-	 *  even though the register is not documented in the Kabini BKDG.
-	 *  Otherwise the serial output is bad code.
-	 */
-	outb(0xD2, 0xcd6);
-	outb(0x00, 0xcd7);
-
 	amd_initmmio();
 
 	/* Set LPC decode enables. */
@@ -62,6 +59,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		post_code(0x30);
 
 		post_code(0x31);
+		fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
 		console_init();
 	}