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GOOGLE/SNOW: add edp support to ramstage

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Add basic edp support to the ramstage. Not working.

Change-Id: I15086e03417edca7426c214e67b51719d8ed9341
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3055
Tested-by: build bot (Jenkins)
This commit is contained in:
Ronald G. Minnich
2013-04-09 14:39:34 -07:00
parent 765ff76d8f
commit 7576f2515e
5 changed files with 217 additions and 28 deletions
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38
src/cpu/samsung/exynos5-common/exynos-fb.c
View File

@@ -203,7 +203,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
video_info->ycbcr_coeff);
if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
debug("PLL is not locked yet.\n");
printk(BIOS_DEBUG, "PLL is not locked yet.\n");
return -ERR_PLL_NOT_UNLOCKED;
}
@@ -216,7 +216,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
} while (get_timer(start) <= STREAM_ON_TIMEOUT);
if (!timeout) {
debug("Video Clock Not ok\n");
printk(BIOS_DEBUG, "Video Clock Not ok\n");
return -ERR_VIDEO_CLOCK_BAD;
}
@@ -236,7 +236,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
timeout = s5p_dp_is_video_stream_on(dp);
if (timeout) {
debug("Video Stream Not on\n");
printk(BIOS_DEBUG, "Video Stream Not on\n");
return -ERR_VIDEO_STREAM_BAD;
}
@@ -253,14 +253,14 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp)
u8 data;
if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data)) {
debug("DPCD read error\n");
printk(BIOS_DEBUG, "DPCD read error\n");
return -ERR_DPCD_READ_ERROR1;
}
if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
DPCD_ENHANCED_FRAME_EN |
(data & DPCD_LANE_COUNT_SET_MASK))) {
debug("DPCD write error\n");
printk(BIOS_DEBUG, "DPCD write error\n");
return -ERR_DPCD_WRITE_ERROR1;
}
@@ -281,13 +281,13 @@ static int s5p_dp_enable_scramble(struct s5p_dp_device *dp)
if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
&data)) {
debug("DPCD read error\n");
printk(BIOS_DEBUG, "DPCD read error\n");
return -ERR_DPCD_READ_ERROR2;
}
if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
(u8)(data & ~DPCD_SCRAMBLING_DISABLED))) {
debug("DPCD write error\n");
printk(BIOS_DEBUG, "DPCD write error\n");
return -ERR_DPCD_WRITE_ERROR2;
}
@@ -314,10 +314,10 @@ static int s5p_dp_init_dp(struct s5p_dp_device *dp)
break;
udelay(5000);
debug("LCD retry init, attempt=%d ret=%d\n", i, ret);
printk(BIOS_DEBUG, "LCD retry init, attempt=%d ret=%d\n", i, ret);
}
if (i == DP_INIT_TRIES) {
debug("LCD initialization failed, ret=%d\n", ret);
printk(BIOS_DEBUG, "LCD initialization failed, ret=%d\n", ret);
return ret;
}
@@ -356,7 +356,7 @@ static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp,
writel(reg, &base->ln3_link_trn_ctl);
break;
default:
debug("%s: Invalid lane %d\n", __func__, lane);
printk(BIOS_DEBUG, "%s: Invalid lane %d\n", __func__, lane);
return -ERR_INVALID_LANE;
}
return 0;
@@ -438,7 +438,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
for (lane = 0; lane < max_lane; lane++)
if (s5p_dp_set_lane_lane_pre_emphasis(dp,
PRE_EMPHASIS_LEVEL_0, lane)) {
debug("Unable to set pre emphasis level\n");
printk(BIOS_DEBUG, "Unable to set pre emphasis level\n");
return -ERR_PRE_EMPHASIS_LEVELS;
}
@@ -451,14 +451,14 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
(dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
debug("Rx Max Link Rate is abnormal :%x !\n",
printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n",
dp->link_train.link_rate);
/* Not Retrying */
return -ERR_LINK_RATE_ABNORMAL;
}
if (dp->link_train.lane_count == 0) {
debug("Rx Max Lane count is abnormal :%x !\n",
printk(BIOS_DEBUG, "Rx Max Lane count is abnormal :%x !\n",
dp->link_train.lane_count);
/* Not retrying */
return -ERR_MAX_LANE_COUNT_ABNORMAL;
@@ -487,7 +487,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
/* Get hardware link training status */
data = readl(&base->dp_hw_link_training);
if (data != 0) {
debug(" H/W link training failure: 0x%x\n", data);
printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data);
return -ERR_LINK_TRAINING_FAILURE;
}
@@ -521,14 +521,14 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
power_enable_dp_phy();
ret = s5p_dp_init_dp(dp);
if (ret) {
debug("%s: Could not initialize dp\n", __func__);
printk(BIOS_DEBUG, "%s: Could not initialize dp\n", __func__);
return ret;
}
ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count,
dp->video_info->link_rate);
if (ret) {
debug("unable to do link train\n");
printk(BIOS_DEBUG, "unable to do link train\n");
return ret;
}
/* Minimum delay after H/w Link training */
@@ -536,13 +536,13 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
ret = s5p_dp_enable_scramble(dp);
if (ret) {
debug("unable to set scramble mode\n");
printk(BIOS_DEBUG, "unable to set scramble mode\n");
return ret;
}
ret = s5p_dp_enable_rx_to_enhanced_mode(dp);
if (ret) {
debug("unable to set enhanced mode\n");
printk(BIOS_DEBUG, "unable to set enhanced mode\n");
return ret;
}
@@ -557,7 +557,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
s5p_dp_init_video(dp);
ret = s5p_dp_config_video(dp, dp->video_info);
if (ret) {
debug("unable to config video\n");
printk(BIOS_DEBUG, "unable to config video\n");
return ret;
}

1
src/cpu/samsung/exynos5-common/s5p-dp-core.h
View File

@@ -250,6 +250,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp,
void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp);
/* startup and init */
struct exynos5_fimd_panel;
void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd);
int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms);
int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase);

18
src/cpu/samsung/exynos5-common/s5p-dp-reg.c
View File

@@ -19,6 +19,8 @@
#include "cpu/samsung/exynos5250/fimd.h"
#include "s5p-dp-core.h"
#include <console/console.h>
void s5p_dp_reset(struct s5p_dp_device *dp)
{
u32 reg;
@@ -127,7 +129,7 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp)
start = get_timer(0);
while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
if (get_timer(start) > PLL_LOCK_TIMEOUT) {
debug("%s: PLL is not locked yet\n", __func__);
printk(BIOS_DEBUG, "%s: PLL is not locked yet\n", __func__);
return -1;
}
}
@@ -174,6 +176,9 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
/* Enable AUX CH operation */
setbits_le32(&base->aux_ch_ctl_2, AUX_EN);
printk(BIOS_DEBUG, "%s: base: 0x%p, &base->aux_ch_ctl_2: 0x%p, aux_ch_ctl_2: 0x%08x\n",
__func__, base, &base->aux_ch_ctl_2, readl(&base->aux_ch_ctl_2));
/* Is AUX CH command reply received? */
reg = readl(&base->dp_int_sta);
while (!(reg & RPLY_RECEIV))
@@ -184,6 +189,7 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
/* Clear interrupt source for AUX CH access error */
reg = readl(&base->dp_int_sta);
printk(BIOS_DEBUG, "%s: dp_int_sta: 0x%02x\n", __func__, reg);
if (reg & AUX_ERR) {
writel(AUX_ERR, &base->dp_int_sta);
return -1;
@@ -192,7 +198,7 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
/* Check AUX CH error access status */
reg = readl(&base->dp_int_sta);
if ((reg & AUX_STATUS_MASK) != 0) {
debug("AUX CH error happens: %d\n\n",
printk(BIOS_DEBUG, "AUX CH error happens: %d\n\n",
reg & AUX_STATUS_MASK);
return -1;
}
@@ -241,7 +247,7 @@ int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp,
if (retval == 0)
break;
else
debug("Aux Transaction fail!\n");
printk(BIOS_DEBUG, "Aux Transaction fail!\n");
}
return retval;
@@ -284,7 +290,7 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
if (retval == 0)
break;
else
debug("Aux Transaction fail!\n");
printk(BIOS_DEBUG, "Aux Transaction fail!\n");
}
/* Read data buffer */
@@ -359,7 +365,7 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
reg = readl(&base->sys_ctl_2);
if (reg & CHA_STA) {
debug("Input stream clk is changing\n");
printk(BIOS_DEBUG, "Input stream clk is changing\n");
return -1;
}
@@ -433,7 +439,7 @@ int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp)
} while (get_timer(start) <= STREAM_ON_TIMEOUT);
if (i != 4) {
debug("s5p_dp_is_video_stream_on timeout\n");
printk(BIOS_DEBUG, "s5p_dp_is_video_stream_on timeout\n");
return -1;
}

1
src/mainboard/google/snow/Kconfig
View File

@@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# select MMCONF_SUPPORT
select EXYNOS_DISPLAYPORT
select CHROMEOS
select DRIVER_TI_TPS65090
config MAINBOARD_DIR
string

187
src/mainboard/google/snow/ramstage.c
View File

@@ -18,13 +18,22 @@
*/
#include <console/console.h>
#include <device/device.h>
#include <device/i2c.h>
#include <drivers/ti/tps65090/tps65090.h>
#include <cbmem.h>
#include <delay.h>
#include <arch/cache.h>
#include <arch/exception.h>
#include <arch/gpio.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/power.h>
#include <arch/cache.h>
#include <cpu/samsung/exynos5-common/i2c.h>
#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
@@ -35,7 +44,8 @@ void hardwaremain(int boot_complete);
void main(void)
{
console_init();
printk(BIOS_INFO, "hello from ramstage; now with deluxe exception handling.\n");
printk(BIOS_INFO,
"hello from ramstage; now with deluxe exception handling.\n");
/* set up coreboot tables */
high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
@@ -54,7 +64,8 @@ void main(void)
dcache_invalidate_all();
dcache_mmu_enable();
/* this is going to move, but we must have it now and we're not sure where */
/* this is going to move, but we must have it now and we're
* not sure where */
exception_init();
const unsigned epll_hz = 192000000;
@@ -68,3 +79,173 @@ void main(void)
hardwaremain(0);
}
/* TODO: transplanted DP stuff, clean up once we have something that works */
static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */
static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */
static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */
static void exynos_dp_bridge_setup(void)
{
exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
gpio_set_value(dp_pd_l, 1);
gpio_cfg_pin(dp_pd_l, EXYNOS_GPIO_OUTPUT);
gpio_set_pull(dp_pd_l, EXYNOS_GPIO_PULL_NONE);
gpio_set_value(dp_rst_l, 0);
gpio_cfg_pin(dp_rst_l, EXYNOS_GPIO_OUTPUT);
gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE);
udelay(10);
gpio_set_value(dp_rst_l, 1);
udelay(90000); /* FIXME: this might be unnecessary */
}
static void exynos_dp_bridge_init(void)
{
/* De-assert PD (and possibly RST) to power up the bridge */
gpio_set_value(dp_pd_l, 1);
gpio_set_value(dp_rst_l, 1);
/*
* We need to wait for 90ms after bringing up the bridge since
* there is a phantom "high" on the HPD chip during its
* bootup. The phantom high comes within 7ms of de-asserting
* PD and persists for at least 15ms. The real high comes
* roughly 50ms after PD is de-asserted. The phantom high
* makes it hard for us to know when the NXP chip is up.
*/
udelay(90000); /* FIXME: this might be unnecessary */
}
static int exynos_dp_hotplug(void)
{
int x = gpio_get_value(dp_hpd);
/* Check HPD. If it's high, we're all good. */
// if (gpio_get_value(dp_hpd))
// return 0;
printk(BIOS_DEBUG, "%s: dp_hpd: 0x%02x\n", __func__, x);
if (x)
return 0;
return -1;
}
static void exynos_dp_reset(void)
{
gpio_set_value(dp_pd_l, 0);
gpio_set_value(dp_rst_l, 0);
/* paranoid delay period (300ms) */
udelay(300 * 1000);
}
#define LCD_T5_DELAY_MS 10
#define LCD_T6_DELAY_MS 10
static void snow_backlight_pwm(void)
{
/*Configure backlight PWM as a simple output high (100% brightness) */
gpio_direction_output(GPIO_B20, 1);
udelay(LCD_T6_DELAY_MS * 1000);
}
static void snow_backlight_en(void)
{
/* * Configure GPIO for LCD_BL_EN */
gpio_direction_output(GPIO_X30, 1);
}
#define TPS69050_BUS 4 /* Snow-specific */
#define FET1_CTRL 0x0f
#define FET6_CTRL 0x14
static void snow_lcd_vdd(void)
{
/* Enable FET6, lcd panel */
tps65090_fet_enable(TPS69050_BUS, FET6_CTRL);
}
static void snow_backlight_vdd(void)
{
/* Enable FET1, backlight */
tps65090_fet_enable(TPS69050_BUS, FET1_CTRL);
udelay(LCD_T5_DELAY_MS * 1000);
}
//static struct video_info smdk5250_dp_config = {
static struct video_info snow_dp_video_info = {
/* FIXME: fix video_info struct to use const for name */
.name = (char *)"eDP-LVDS NXP PTN3460",
.h_sync_polarity = 0,
.v_sync_polarity = 0,
.interlaced = 0,
.color_space = COLOR_RGB,
.dynamic_range = VESA,
.ycbcr_coeff = COLOR_YCBCR601,
.color_depth = COLOR_8,
.link_rate = LINK_RATE_2_70GBPS,
.lane_count = LANE_COUNT2,
};
/* FIXME: move some place more appropriate */
#define EXYNOS5250_DP1_BASE 0x145b0000
#define SNOW_MAX_DP_TRIES 5
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
int dp_tries;
unsigned int wait_ms;
struct s5p_dp_device dp_device = {
.base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE,
.video_info = &snow_dp_video_info,
};
i2c_init(TPS69050_BUS, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
i2c_init(7, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
snow_lcd_vdd();
do {
udelay(50);
} while (!exynos_dp_hotplug());
exynos_dp_bridge_setup();
for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) {
if (wait_ms) {
udelay(wait_ms);
wait_ms = 0;
}
exynos_dp_bridge_init();
if (exynos_dp_hotplug()) {
exynos_dp_reset();
continue;
}
if (dp_controller_init(&dp_device, &wait_ms))
continue;
snow_backlight_vdd();
snow_backlight_pwm();
snow_backlight_en();
/* if we're here, we're successful */
break;
}
if (dp_tries > SNOW_MAX_DP_TRIES)
printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__);
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
}
struct chip_operations mainboard_ops = {
.name = "Samsung/Google ARM Chromebook",
.enable_dev = mainboard_enable,
};