YhLu's patch from January 18th. This part is mostly cleaning up
dead code and adding a few fixmes. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Ed Swierk <eswierk@arastra.com> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ward Vandewege <ward@gnu.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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committed by
Stefan Reinauer
parent
47cb7c71c9
commit
75812a66bb
@@ -485,6 +485,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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* [31:26] Reserved
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*/
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PCI_ADDR(0, 0x18, 2, 0x98), 0xfc00ffff, 0x00000000,
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/* MCA NB Status Low reg */
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PCI_ADDR(0, 0x18, 3, 0x48), 0x00f00000, 0x00000000,
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/* MCA NB Status high reg */
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PCI_ADDR(0, 0x18, 3, 0x4c), 0x01801e8c, 0x00000000,
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/* MCA NB address Low reg */
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PCI_ADDR(0, 0x18, 3, 0x50), 0x00000007, 0x00000000,
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/* MCA NB address high reg */
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PCI_ADDR(0, 0x18, 3, 0x54), 0xffffff00, 0x00000000,
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/* DRAM Scrub Control Register
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* F3:0x58
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* [ 4: 0] DRAM Scrube Rate
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@@ -2334,6 +2342,16 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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/* And if necessary toggle the the reset on the dimms by hand */
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memreset(controllers, ctrl);
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/* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */
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#if 0
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print_debug("prepare to InitDram:");
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for(i=0; i<100; i++) {
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print_debug_hex32(i);
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print_debug("\b\b\b\b\b\b\b\b");
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}
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print_debug("\r\n");
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#endif
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for(i = 0; i < controllers; i++) {
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uint32_t dcl, dch;
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if (!controller_present(ctrl + i))
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