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soc/intel/alderlake/fsp_params.c: Set DdrSpeedControl UPD

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When override "max_dram_speed_mts", set the DdrSpeedControl to manual.
(0:Auto, 1:Manual)

BUG=b:229549930
BRANCH=none
TEST=build coreboot without error

Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com>
Change-Id: Iffbbee8082fb1a41e0ed1db3f4ea9ec4709c9ce7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65877
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Franklin Lin
2022-07-15 17:53:13 +08:00
committed by Felix Held
parent e69851cd8a
commit 759bb4c00d
1 changed files with 3 additions and 1 deletions
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4
src/soc/intel/alderlake/romstage/fsp_params.c
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@ -150,8 +150,10 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
{ {
m_cfg->SaGv = config->sagv; m_cfg->SaGv = config->sagv;
m_cfg->RMT = config->RMT; m_cfg->RMT = config->RMT;
if (config->max_dram_speed_mts) if (config->max_dram_speed_mts) {
m_cfg->DdrFreqLimit = config->max_dram_speed_mts; m_cfg->DdrFreqLimit = config->max_dram_speed_mts;
m_cfg->DdrSpeedControl = 1;
}
} }
static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,