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soc/intel/alderlake: add chipset devicetree for ADL-S

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Add chipset devicetree and power limits for AlderLake-S platform.

Based on Intel docs #619501, #619362 and #626343.

Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
This commit is contained in:
Michał Kopeć
2022-04-08 11:28:45 +02:00
committed by Michał Żygowski
parent a08f509cc5
commit 75a49fe856
4 changed files with 245 additions and 1 deletions
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5
src/soc/intel/alderlake/fsp_params.c
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@@ -599,6 +599,11 @@ static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,
s_cfg->PavpEnable = CONFIG(PAVP);
}
WEAK_DEV_PTR(tcss_usb3_port1);
WEAK_DEV_PTR(tcss_usb3_port2);
WEAK_DEV_PTR(tcss_usb3_port3);
WEAK_DEV_PTR(tcss_usb3_port4);
static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{