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intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP

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Change-Id: Ib3250677ee926deaa957c83aca7479eb0159358c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15231
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2016-06-17 10:00:28 +03:00
parent 8431fcb8c8
commit 75d139bdf2
3 changed files with 13 additions and 3 deletions
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1
src/cpu/intel/model_206ax/Makefile.inc
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@@ -10,3 +10,4 @@ cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
romstage-y += ../car/romstage.c

10
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@@ -172,7 +172,12 @@ clear_mtrrs:
before_romstage:
post_code(0x29)
/* Call romstage.c main function. */
call main
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down.
*/
movl %eax, %ebx
post_code(0x2f)
@@ -303,7 +308,8 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $CONFIG_RAMTOP, %esp
/* Setup stack as indicated by return value from romstage_main(). */
movl %ebx, %esp
movl %esp, %ebp
call copy_and_run