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coreboot: config to cache ramstage outside CBMEM

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Haswell was the original chipset to store the cache
in another area besides CBMEM. However, it was specific
to the implementation. Instead, provide a generic way
to obtain the location of the ramstage cache. This option
is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Kconfig option.

BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted with baytrail support. Also built for
     falco successfully.

Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172602
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4876
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Aaron Durbin
2013-10-10 20:37:04 -05:00
committed by Aaron Durbin
parent 6ac3405fdf
commit 75e297428f
7 changed files with 213 additions and 119 deletions
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16
src/cpu/intel/haswell/haswell.h
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@@ -215,22 +215,6 @@ void release_aps_for_smm_relocation(int do_parallel_relocation);
extern int ht_disabled;
#endif
/* This structure is saved along with the relocated ramstage program in SMM
* space. It is used to protect the integrity of the ramstage program on S3
* resume by saving a copy of the relocated ramstage in SMM space with the
* assumption that the SMM region cannot be altered from the OS. The magic
* value just serves as a quick sanity check. */
#define RAMSTAGE_CACHE_MAGIC 0xf3c3a02a
struct ramstage_cache {
uint32_t magic;
uint32_t entry_point;
uint32_t load_address;
uint32_t size;
char program[0];
} __attribute__((packed));
/* CPU identification */
int haswell_family_model(void);
int haswell_stepping(void);