mb/amd/birman: Move EC FW to FMAP
Move EC FW from a CBFS file to an FMAP entry and rename the EC signature section to EC_SIG. An offset of (16M - 512K) was chosen to line up the EC FW before the RW_MRC_CACHE. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9b19d92043790b10acd20fbfdf394d5bd67b8295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
committed by
Lean Sheng Tan
parent
36ca7b3104
commit
75e720bf02
@@ -51,17 +51,7 @@ config BIRMAN_MCHP_FW_FILE
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depends on BIRMAN_HAVE_MCHP_FW
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depends on BIRMAN_HAVE_MCHP_FW
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default "3rdparty/blobs/mainboard/amd/birman/EC_birman.bin"
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default "3rdparty/blobs/mainboard/amd/birman/EC_birman.bin"
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help
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help
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The EC firmware blob is at the BIRMAN_MCHP_FW_OFFSET offset of the
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The EC firmware blob is at the EC_BODY FMAP region of the firmware image.
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firmware image.
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config BIRMAN_MCHP_FW_OFFSET
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hex
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depends on BIRMAN_HAVE_MCHP_FW
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default 0xF00000
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help
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The EC firmware blob defaults to the 4MByte offset of the firmware
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image. If this offset needs to change, a new signature block must be
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generated with the updated offset.
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config VBOOT
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config VBOOT
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select VBOOT_NO_BOARD_SUPPORT
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select VBOOT_NO_BOARD_SUPPORT
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@@ -19,12 +19,8 @@ endif
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ifeq ($(CONFIG_BIRMAN_HAVE_MCHP_FW),y)
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ifeq ($(CONFIG_BIRMAN_HAVE_MCHP_FW),y)
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$(call add_intermediate, add_mchp_fw)
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$(call add_intermediate, add_mchp_fw)
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$(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_BIRMAN_MCHP_SIG_FILE) --fill-upward
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$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_SIG -f $(CONFIG_BIRMAN_MCHP_SIG_FILE) --fill-upward
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$(CBFSTOOL) $(obj)/coreboot.pre write -r EC_BODY -f $(CONFIG_BIRMAN_MCHP_FW_FILE) --fill-upward
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cbfs-files-y += apu/ecfw
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apu/ecfw-file := $(CONFIG_BIRMAN_MCHP_FW_FILE)
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apu/ecfw-position := $(CONFIG_BIRMAN_MCHP_FW_OFFSET)
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apu/ecfw-type := raw
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else
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else
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files_added:: warn_no_mchp
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files_added:: warn_no_mchp
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@@ -1,8 +1,9 @@
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FLASH@0xFF000000 16M {
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FLASH@0xFF000000 16M {
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BIOS {
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BIOS {
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EC 4K
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EC_SIG 4K
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FMAP 4K
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FMAP 4K
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COREBOOT(CBFS)
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COREBOOT(CBFS)
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EC_BODY@15872K 256K
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RW_MRC_CACHE 120K
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RW_MRC_CACHE 120K
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}
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}
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}
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}
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@@ -1,8 +1,9 @@
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FLASH@0xFF000000 16M {
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FLASH@0xFF000000 16M {
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BIOS {
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BIOS {
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EC 4K
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EC_SIG 4K
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FMAP 4K
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FMAP 4K
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COREBOOT(CBFS)
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COREBOOT(CBFS)
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EC_BODY@15872K 256K
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RW_MRC_CACHE 256K
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RW_MRC_CACHE 256K
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}
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}
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}
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}
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@@ -1,7 +1,7 @@
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FLASH@0xFF000000 16M {
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FLASH@0xFF000000 16M {
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SI_BIOS {
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SI_BIOS {
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WP_RO 8M {
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WP_RO 8M {
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EC 4K
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EC_SIG 4K
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RO_VPD(PRESERVE) 16K
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RO_VPD(PRESERVE) 16K
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RO_SECTION {
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RO_SECTION {
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FMAP 2K
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FMAP 2K
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@@ -29,6 +29,7 @@ FLASH@0xFF000000 16M {
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RW_NVRAM(PRESERVE) 20K
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RW_NVRAM(PRESERVE) 20K
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SMMSTORE(PRESERVE) 64K
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SMMSTORE(PRESERVE) 64K
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RW_LEGACY(CBFS)
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RW_LEGACY(CBFS)
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EC_BODY@15872K 256K
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RW_MRC_CACHE(PRESERVE) 120K
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RW_MRC_CACHE(PRESERVE) 120K
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}
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}
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}
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}
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@@ -1,7 +1,7 @@
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FLASH@0xFF000000 16M {
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FLASH@0xFF000000 16M {
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SI_BIOS {
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SI_BIOS {
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WP_RO 8M {
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WP_RO 8M {
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EC 4K
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EC_SIG 4K
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RO_VPD(PRESERVE) 16K
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RO_VPD(PRESERVE) 16K
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RO_SECTION {
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RO_SECTION {
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FMAP 2K
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FMAP 2K
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@@ -29,6 +29,7 @@ FLASH@0xFF000000 16M {
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RW_NVRAM(PRESERVE) 20K
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RW_NVRAM(PRESERVE) 20K
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SMMSTORE(PRESERVE) 64K
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SMMSTORE(PRESERVE) 64K
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RW_LEGACY(CBFS)
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RW_LEGACY(CBFS)
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EC_BODY@15872K 256K
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RW_MRC_CACHE(PRESERVE) 256K
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RW_MRC_CACHE(PRESERVE) 256K
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}
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}
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}
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}
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