soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver

commit ce0e2a0140 (drivers/intel/fsp2_0:
use FSP to allocate APEI BERT memory region) adds a mechanism to reserve
the BERT region inside the coreboot code, so we can get rid of the
workaround to reserve it in the FSP and return the location in a HOB.
mcfg->bert_size defaults to 0 which makes the FSP not generate the
corresponding HOB, but that field is planned to be removed at least on
Cezanne, so don't explicitly set it to 0.

BUG=b:169934025
TEST=BERT table that gets generated in a follow-up patch for Picasso
points to expected BERT region and Linux is able to access, decode and
display it.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaca89b47793bf9982181560f026459a18e7db134
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/amd/fsp/cezanne/FspGuids.h

@@ -9,10 +9,6 @@
 		GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \
 		0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c)
 
-#define AMD_FSP_BERT_HOB_GUID \
-		GUID_INIT(0xa21f7ab5, 0x6a89, 0x4df2, \
-		0xb9, 0x19, 0x51, 0xad, 0x95, 0x50, 0x5b, 0xd8)
-
 #define AMD_FSP_ACPI_ALIB_HOB_GUID \
 		GUID_INIT(0x42494c41, 0x4002, 0x403b, \
 		0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A)

src/vendorcode/amd/fsp/picasso/FspGuids.h

@@ -9,10 +9,6 @@
 		GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \
 		0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c)
 
-#define AMD_FSP_BERT_HOB_GUID \
-		GUID_INIT(0xa21f7ab5, 0x6a89, 0x4df2, \
-		0xb9, 0x19, 0x51, 0xad, 0x95, 0x50, 0x5b, 0xd8)
-
 #define AMD_FSP_ACPI_SSDT_HOB_GUID \
 		GUID_INIT(0x54445353, 0x4002, 0x403b, \
 		0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A)