diff --git a/src/mainboard/system76/oryp4/Kconfig b/src/mainboard/system76/oryp4/Kconfig new file mode 100644 index 0000000000..77a4dd19f6 --- /dev/null +++ b/src/mainboard/system76/oryp4/Kconfig @@ -0,0 +1,52 @@ +if BOARD_SYSTEM76_ORYP4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + default "system76/oryp4" + +config MAINBOARD_PART_NUMBER + default "oryp4" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Oryx Pro" + +config MAINBOARD_VERSION + default "oryp4" + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config ONBOARD_VGA_IS_PRIMARY + default y + +config UART_FOR_CONSOLE + default 2 + +config DIMM_MAX + default 2 + +config POST_DEVICE + default n + +endif diff --git a/src/mainboard/system76/oryp4/Kconfig.name b/src/mainboard/system76/oryp4/Kconfig.name new file mode 100644 index 0000000000..aabbbed701 --- /dev/null +++ b/src/mainboard/system76/oryp4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SYSTEM76_ORYP4 + bool "oryp4" diff --git a/src/mainboard/system76/oryp4/Makefile.inc b/src/mainboard/system76/oryp4/Makefile.inc new file mode 100644 index 0000000000..83ef3a5ca8 --- /dev/null +++ b/src/mainboard/system76/oryp4/Makefile.inc @@ -0,0 +1,8 @@ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +ramstage-y += ramstage.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/system76/oryp4/acpi/gpe.asl b/src/mainboard/system76/oryp4/acpi/gpe.asl new file mode 100644 index 0000000000..81022642e4 --- /dev/null +++ b/src/mainboard/system76/oryp4/acpi/gpe.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// GPP_B23 SCI +Method (_L17, 0, Serialized) +{ + Debug = Concatenate("GPE _L17: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == 1) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/system76/oryp4/acpi/mainboard.asl b/src/mainboard/system76/oryp4/acpi/mainboard.asl new file mode 100644 index 0000000000..4373b2a4a1 --- /dev/null +++ b/src/mainboard/system76/oryp4/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x17 /* GPP_B23 */ +#define EC_GPE_SWI 0x26 /* GPP_G6 */ +#include + +Scope (\_SB) +{ + #include "sleep.asl" +} + +Scope (\_GPE) +{ + #include "gpe.asl" +} diff --git a/src/mainboard/system76/oryp4/acpi/sleep.asl b/src/mainboard/system76/oryp4/acpi/sleep.asl new file mode 100644 index 0000000000..f2b194c422 --- /dev/null +++ b/src/mainboard/system76/oryp4/acpi/sleep.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/system76/oryp4/board_info.txt b/src/mainboard/system76/oryp4/board_info.txt new file mode 100644 index 0000000000..1d0a5a6a13 --- /dev/null +++ b/src/mainboard/system76/oryp4/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: oryp4 +Category: laptop +Release year: 2018 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/oryp4/bootblock.c b/src/mainboard/system76/oryp4/bootblock.c new file mode 100644 index 0000000000..8d06adc9d7 --- /dev/null +++ b/src/mainboard/system76/oryp4/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/system76/oryp4/cmos.default b/src/mainboard/system76/oryp4/cmos.default new file mode 100644 index 0000000000..57750a2029 --- /dev/null +++ b/src/mainboard/system76/oryp4/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +power_on_after_fail=Enable +debug_level=Debug diff --git a/src/mainboard/system76/oryp4/cmos.layout b/src/mainboard/system76/oryp4/cmos.layout new file mode 100644 index 0000000000..ca7c7a4c5c --- /dev/null +++ b/src/mainboard/system76/oryp4/cmos.layout @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +409 2 e 7 power_on_after_fail +412 4 e 6 debug_level +984 16 h 0 check_sum + +enumerations + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +7 0 Disable +7 1 Enable +7 2 Keep + +checksums + +checksum 408 983 984 diff --git a/src/mainboard/system76/oryp4/data.vbt b/src/mainboard/system76/oryp4/data.vbt new file mode 100644 index 0000000000..e41aba6d11 Binary files /dev/null and b/src/mainboard/system76/oryp4/data.vbt differ diff --git a/src/mainboard/system76/oryp4/devicetree.cb b/src/mainboard/system76/oryp4/devicetree.cb new file mode 100644 index 0000000000..c3fa2278b5 --- /dev/null +++ b/src/mainboard/system76/oryp4/devicetree.cb @@ -0,0 +1,148 @@ +chip soc/intel/cannonlake + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 78, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console + }" + + # Misc + register "AcousticNoiseMitigation" = "1" + + # TODO: Copied from oryp5 + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "4" # 4s + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "13" + + # Serial IRQ Continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # TODO: Copied from oryp5 + register "gpe0_dw0" = "PMC_GPP_B" + register "gpe0_dw1" = "PMC_GPP_G" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + # TODO: SSID + #subsystemid 0x1558 inherit + device pci 00.0 on end # Host Bridge + device pci 01.0 on # GPU Port + # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) + register "PcieClkSrcUsage[8]" = "0x40" + register "PcieClkSrcClkReq[8]" = "8" + end + device pci 02.0 on # Integrated Graphics Device + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device pci 04.0 on # SA Thermal device + register "Device4Enable" = "1" + end + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Shared SRAM + device pci 14.3 on end # CNVi wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1b.0 off end # PCI Express Port 17 + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1b.4 off end # PCI Express Port 21 + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0e01" + register "gen3_dec" = "0x00fc0f01" + #chip drivers/pc80/tpm + # TODO + #end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on # Intel HDA + # TODO: SSID + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/system76/oryp4/dsdt.asl b/src/mainboard/system76/oryp4/dsdt.asl new file mode 100644 index 0000000000..982e226118 --- /dev/null +++ b/src/mainboard/system76/oryp4/dsdt.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } + + #include + + Scope (\_SB.PCI0.LPCB) + { + #include + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/oryp4/gpio.c b/src/mainboard/system76/oryp4/gpio.c new file mode 100644 index 0000000000..995ad3c97a --- /dev/null +++ b/src/mainboard/system76/oryp4/gpio.c @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + PAD_NC(GPD0, NONE), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT + PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUBC#_PCH + PAD_NC(GPD6, NONE), // SLP_A# + PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7: crystal input + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // PCH_SUSCLK + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_ADC0 + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_ADC1 + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_ADC2 + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_ADC3 + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ + PAD_NC(GPP_A7, NONE), // LPC_PIRQA# + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // PCLK_TPM + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), // SUSWARN# + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), // SUS_PWR_ACK# + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + PAD_CFG_GPO(GPP_A19, 1, DEEP), // SB_BLON + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + PAD_NC(GPP_B0, NONE), + PAD_NC(GPP_B1, NONE), + PAD_NC(GPP_B2, NONE), + PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN + PAD_CFG_GPO(GPP_B4, 1, DEEP), // WLAN_EN + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), // LPSS_GSPI0_MOSI + PAD_NC(GPP_B19, NONE), + _PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000), // SMI# + PAD_NC(GPP_B21, NONE), + PAD_CFG_GPI(GPP_B22, NONE, DEEP), // LPSS_GSPI1_MOSI: LPC boot strap + _PAD_CFG_STRUCT(GPP_B23, 0x80880100, 0x3000), // SCI# + + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK / SMC_ASM1562 + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA / SMD_ASM1562 + PAD_CFG_GPI(GPP_C2, NONE, DEEP), // GPP_C2_BT_UART_WAKE_N + PAD_NC(GPP_C3, NONE), + PAD_NC(GPP_C4, NONE), + PAD_CFG_GPO(GPP_C5, 1, DEEP), // M.2_WLAN_WIFI_WAKE_N + PAD_NC(GPP_C6, NONE), // SMC_CPU_THERM + PAD_NC(GPP_C7, NONE), // SMD_CPU_THERM + PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET + PAD_CFG_GPI(GPP_C9, DN_20K, DEEP), // BOARD_ID1 + PAD_CFG_GPI(GPP_C10, DN_20K, DEEP), // BOARD_ID2 + PAD_CFG_GPI(GPP_C11, DN_20K, DEEP), // BOARD_ID3 + PAD_CFG_GPI(GPP_C12, NONE, DEEP), // GC6_FB_EN_PCH + PAD_CFG_GPO(GPP_C13, 1, DEEP), // GPU_EVENT# + PAD_CFG_GPO(GPP_C14, 1, DEEP), // M.2_PLT_RST_CNTRL1_N + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD + PAD_NC(GPP_C22, NONE), // UART2_RTS# + PAD_NC(GPP_C23, NONE), // UART2_CTS# + + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // M.2_BT_PCMFRM_CRF_RST_N + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // M.2_BT_PCMOUT_CLKREQ0 + PAD_CFG_GPI(GPP_D7, NONE, DEEP), // M.2_BT_PCMIN + PAD_CFG_GPO(GPP_D8, 1, DEEP), // M.2_BT_PCMCLK + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + PAD_NC(GPP_E0, NONE), + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_PEDET + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_CFG_GPO(GPP_E5, 1, DEEP), // M2_P0_SATA_DEVSLP + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED# + PAD_NC(GPP_E9, NONE), // USB_OC0# + PAD_NC(GPP_E10, NONE), // USB_OC1# + PAD_NC(GPP_E11, NONE), // USB_OC2# + PAD_NC(GPP_E12, NONE), // USB_OC3# + + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), // SATAGP4 + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // LIGHT_KB_DET# + PAD_NC(GPP_F7, NONE), // MHDD_SATA_DEVSLP + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC: BIOS recovery enable strap + PAD_CFG_GPI(GPP_F11, NONE, DEEP), // GPP_F11: reserved strap + PAD_NC(GPP_F12, NONE), + PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GP39_GFX_CRB_DETECT: GFX select table strap + PAD_CFG_GPI(GPP_F14, NONE, DEEP), // H_SKTOCC_N + PAD_NC(GPP_F15, NONE), // USB_OC4# + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), // USB_OC7# + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN + + PAD_NC(GPP_G0, NONE), + PAD_CFG_GPI(GPP_G1, NONE, DEEP), // CNVI_WIGIG_DET# + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + _PAD_CFG_STRUCT(GPP_G6, 0x40880100, 0x0000), // SWI# + PAD_NC(GPP_G7, NONE), + + PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H1, NONE), + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // CLK_REQ9_PEG# + PAD_NC(GPP_H3, NONE), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CLK_REQ13_SSD1# + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // GPP_H_0_SRCCLKREQB_14 + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CLK_REQ15_LAN# + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CLK_REQ16_CARD# + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), // GPP_H_12: ESPI FLASH SHARING MODE + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), // GPP_H15: reserved strap + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_NC(GPP_H18, NONE), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), // GPP_H21 + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + _PAD_CFG_STRUCT(GPP_I0, 0x46880100, 0x0000), // G_DP_DHPD_F + _PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // HDMI_HPD + _PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // G_DP_DHPD_E + PAD_NC(GPP_I3, NONE), + PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, NONE), + PAD_CFG_GPI(GPP_I11, NONE, DEEP), // H_SKTOCC_N + PAD_NC(GPP_I12, NONE), + PAD_NC(GPP_I13, NONE), + PAD_NC(GPP_I14, NONE), + + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + _PAD_CFG_STRUCT(GPP_J1, 0x44000a01, 0x0000), // GPP_J1 + PAD_NC(GPP_J2, NONE), + PAD_NC(GPP_J3, NONE), + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // M.2_CNV_BRI_DT + PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), // M.2_CNV_BRI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // M.2_CNV_RGI_DT + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // M.2_CNV_RGI_RSP + PAD_NC(GPP_J8, NONE), + PAD_CFG_GPI(GPP_J9, NONE, DEEP), // CNVI_MFUART2_TXD: VCCPSPI voltage select + PAD_NC(GPP_J10, NONE), + PAD_NC(GPP_J11, NONE), + + PAD_NC(GPP_K0, NONE), + PAD_NC(GPP_K1, NONE), + PAD_NC(GPP_K2, NONE), + PAD_NC(GPP_K3, NONE), + PAD_NC(GPP_K4, NONE), + PAD_NC(GPP_K5, NONE), + PAD_NC(GPP_K6, NONE), + PAD_NC(GPP_K7, NONE), + PAD_CFG_GPO(GPP_K8, 1, DEEP), // SATA_M2_PWR_EN + PAD_NC(GPP_K9, NONE), + PAD_NC(GPP_K10, NONE), + PAD_NC(GPP_K11, NONE), + PAD_NC(GPP_K12, NONE), + PAD_NC(GPP_K13, NONE), + PAD_CFG_GPI(GPP_K14, NONE, DEEP), // GPP_K_14_GSXDIN: DMI AC coupling full voltage + PAD_NC(GPP_K15, NONE), + PAD_NC(GPP_K16, NONE), + PAD_NC(GPP_K17, NONE), + PAD_NC(GPP_K18, NONE), + PAD_NC(GPP_K19, NONE), + PAD_NC(GPP_K20, NONE), + PAD_NC(GPP_K21, NONE), + PAD_NC(GPP_K22, NONE), + PAD_NC(GPP_K23, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/oryp4/gpio_early.c b/src/mainboard/system76/oryp4/gpio_early.c new file mode 100644 index 0000000000..80f37c6553 --- /dev/null +++ b/src/mainboard/system76/oryp4/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/oryp4/hda_verb.c b/src/mainboard/system76/oryp4/hda_verb.c new file mode 100644 index 0000000000..52b0bca780 --- /dev/null +++ b/src/mainboard/system76/oryp4/hda_verb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x155896e1, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x155896e1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11050), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), + AZALIA_PIN_CFG(0, 0x1e, 0x04451130), +}; + +const u32 pc_beep_verbs[] = { + // Enable DMIC microphone on ALC1220 + 0x02050036, + 0x02042a6a, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/oryp4/include/mainboard/gpio.h b/src/mainboard/system76/oryp4/include/mainboard/gpio.h new file mode 100644 index 0000000000..c6393beebb --- /dev/null +++ b/src/mainboard/system76/oryp4/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/oryp4/ramstage.c b/src/mainboard/system76/oryp4/ramstage.c new file mode 100644 index 0000000000..43ee54f50a --- /dev/null +++ b/src/mainboard/system76/oryp4/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/system76/oryp4/romstage.c b/src/mainboard/system76/oryp4/romstage.c new file mode 100644 index 0000000000..02634ba2ad --- /dev/null +++ b/src/mainboard/system76/oryp4/romstage.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct cnl_mb_cfg memcfg = { + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .rcomp_resistor = { 121, 75, 100 }, + .rcomp_targets = { 50, 25, 20, 20, 26 }, + .dq_pins_interleaved = 1, + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +}