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Update LPC and GPE config

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This commit is contained in:
Jeremy Soller
2019-05-10 11:03:24 -06:00
parent 747364169f
commit 764d87a6d4
1 changed files with 9 additions and 9 deletions
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18
src/mainboard/system76/cfl-h/devicetree.cb
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@@ -149,14 +149,14 @@ chip soc/intel/cannonlake
# LPC (soc/intel/cannonlake/lpc.c) # LPC (soc/intel/cannonlake/lpc.c)
# LPC configuration from lspci -s 1f.0 -xxx # LPC configuration from lspci -s 1f.0 -xxx
# Address 0x84: Decode 0x80 - 0x8F # Address 0x84: TODO
register "gen1_dec" = "0x000c0081" register "gen1_dec" = "0x000c1641"
# Address 0x88: Decode 0x68 - 0x6F # Address 0x88: TODO
register "gen2_dec" = "0x00040069" register "gen2_dec" = "0x000c0681"
# Address 0x8C: Decode 0x3320 - 0x332F # Address 0x8C: Decode 0x80 - 0x8F
register "gen3_dec" = "0x000c3321" register "gen3_dec" = "0x000c0081"
# Address 0x90: Disabled # Address 0x90: Decode 0x68 - 0x6F
register "gen4_dec" = "0x00000000" register "gen4_dec" = "0x00040069"
# 8254 # 8254
register "clock_gate_8254" = "0" register "clock_gate_8254" = "0"
@@ -175,7 +175,7 @@ chip soc/intel/cannonlake
# route. i.e. If this route changes then the affected GPE # route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed. # offset bits also need to be changed.
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
register "gpe0_dw0" = "PMC_GPP_C" register "gpe0_dw0" = "PMC_GPP_K"
register "gpe0_dw1" = "PMC_GPP_D" register "gpe0_dw1" = "PMC_GPP_D"
register "gpe0_dw2" = "PMC_GPP_E" register "gpe0_dw2" = "PMC_GPP_E"