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mb/google/sarien: Add settings for noise mitgation

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Enable acoustic noise mitgation for sarien platform, the slow slew rates
are fast time dived by 8.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I5d38a1e03af08f106e2422a319b34c3fb54bdf28
Reviewed-on: https://review.coreboot.org/c/30448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Lijian Zhao
2018-12-26 19:53:32 -08:00
committed by Duncan Laurie
parent dff185a28d
commit 768cd37bc3
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/sarien/variants/sarien/devicetree.cb
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@@ -33,6 +33,11 @@ chip soc/intel/cannonlake
register "dptf_enable" = "1" register "dptf_enable" = "1"
register "dmipwroptimize" = "1" register "dmipwroptimize" = "1"
register "satapwroptimize" = "1" register "satapwroptimize" = "1"
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRateForIa" = "2"
register "SlowSlewRateForGt" = "2"
register "SlowSlewRateForSa" = "2"
register "SlowSlewRateForFivr" = "2"
# Intel Common SoC Config # Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port