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soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig

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The devicetree is not made for user-choosable options, thus introduce
Kconfig options for both SGX and the corresponding PRMRR size.

The PRMRR size Kconfig has been implemented as a maximum value. At
runtime the final PRMRR size gets selected by checking the supported
values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest
to the chosen one.

When "Maximum" is chosen, the highest possibly value from the MSR gets
used. When a too strict limit is set, coreboot will die, printing an
error message.

Tested successfully on X11SSM-F

Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner
2019-10-22 23:05:06 +02:00
committed by Nico Huber
parent e75a64f822
commit 7736bfc443
25 changed files with 130 additions and 82 deletions
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1
src/soc/intel/apollolake/Makefile.inc
View File

@@ -1,5 +1,6 @@
ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
subdirs-y += ../../../cpu/intel/common
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic

12
src/soc/intel/apollolake/chip.h
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@@ -139,18 +139,6 @@ struct soc_intel_apollolake_config {
/* GPIO SD card detect pin */
unsigned int sdcard_cd_gpio;
/* PRMRR size setting with three options
* 0x02000000 - 32MiB
* 0x04000000 - 64MiB
* 0x08000000 - 128MiB */
uint32_t PrmrrSize;
/* Enable SGX feature.
* Enabling SGX feature is 2 step process,
* (1) set sgx_enable = 1
* (2) set PrmrrSize to supported size */
uint8_t sgx_enable;
/* Select PNP Settings.
* (0) Performance,
* (1) Power

11
src/soc/intel/apollolake/cpu.c
View File

@@ -72,13 +72,10 @@ static const struct reg_script core_msr_script[] = {
void soc_core_init(struct device *cpu)
{
config_t *conf = config_of_soc();
/* Clear out pending MCEs */
/* TODO(adurbin): Some of these banks are core vs package
scope. For now every CPU clears every bank. */
if ((CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) ||
acpi_get_sleep_type() == ACPI_S5)
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) || acpi_get_sleep_type() == ACPI_S5)
mca_configure();
/* Set core MSRs */
@@ -91,7 +88,7 @@ void soc_core_init(struct device *cpu)
enable_pm_timer_emulation();
/* Configure Core PRMRR for SGX. */
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable)
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
prmrr_core_configure();
/* Set Max Non-Turbo ratio if RAPL is disabled. */
@@ -255,11 +252,9 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
static void post_mp_init(void)
{
config_t *conf = config_of_soc();
smm_southbridge_enable(PWRBTN_EN | GBL_EN);
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable)
if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
mp_run_on_all_cpus(sgx_configure, NULL);
}

7
src/soc/intel/apollolake/memmap.c
View File

@@ -16,23 +16,20 @@
*/
#include <cbmem.h>
#include <intelblocks/cpulib.h>
#include <soc/systemagent.h>
#include "chip.h"
void *cbmem_top_chipset(void)
{
const config_t *config;
void *tolum = (void *)sa_get_tseg_base();
if (!CONFIG(SOC_INTEL_GLK))
return tolum;
config = config_of_soc();
/* FSP allocates 2x PRMRR Size Memory for alignment */
if (config->sgx_enable)
tolum -= config->PrmrrSize * 2;
tolum -= get_prmrr_size() * 2;
return tolum;
}

4
src/soc/intel/apollolake/romstage.c
View File

@@ -269,9 +269,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
/* Only for GLK */
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
const config_t *config = config_of_soc();
m_cfg->PrmrrSize = config->PrmrrSize;
m_cfg->PrmrrSize = get_prmrr_size();
/*
* CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init.