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src/drivers: Capitalize CPU, RAM and ACPI

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Change-Id: I720469ea1df75544f5b1e0cab718502d8a9cf197
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15983
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS
2016-07-30 15:37:26 +02:00
committed by Martin Roth
parent 038e7247dc
commit 7753731f0c
7 changed files with 8 additions and 8 deletions
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2
src/drivers/i2c/w83795/w83795.c
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@ -361,7 +361,7 @@ static void w83795_hwm_init(struct device *dev)
info = cpu_info(); info = cpu_info();
cpu = info->cpu; cpu = info->cpu;
if (!cpu) if (!cpu)
die("CPU: missing cpu device structure"); die("CPU: missing CPU device structure");
if (cpu->vendor == X86_VENDOR_AMD) if (cpu->vendor == X86_VENDOR_AMD)
w83795_init(dev, THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI); w83795_init(dev, THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI);

2
src/drivers/intel/fsp1_1/cache_as_ram.inc
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@ -154,7 +154,7 @@ before_romstage:
call cache_as_ram_main call cache_as_ram_main
/* One will never return from cache_as_ram_main() in verstage so there's /* One will never return from cache_as_ram_main() in verstage so there's
* no such thing as after ram init. */ * no such thing as after RAM init. */
#if !ENV_VERSTAGE #if !ENV_VERSTAGE
#include "after_raminit.S" #include "after_raminit.S"
#endif #endif

4
src/drivers/intel/fsp1_1/car.c
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@ -69,7 +69,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
set_fih_car(car_params->fih); set_fih_car(car_params->fih);
/* Return new stack value in ram back to assembly stub. */ /* Return new stack value in RAM back to assembly stub. */
return cache_as_ram_stage_main(car_params->fih); return cache_as_ram_stage_main(car_params->fih);
} }
@ -93,7 +93,7 @@ asmlinkage void *romstage_after_verstage(void)
set_fih_car(fih); set_fih_car(fih);
/* Return new stack value in ram back to assembly stub. */ /* Return new stack value in RAM back to assembly stub. */
return cache_as_ram_stage_main(fih); return cache_as_ram_stage_main(fih);
} }

2
src/drivers/intel/fsp1_1/include/fsp/car.h
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@ -34,7 +34,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
asmlinkage void after_cache_as_ram(void *chipset_context); asmlinkage void after_cache_as_ram(void *chipset_context);
asmlinkage void *romstage_after_verstage(void); asmlinkage void *romstage_after_verstage(void);
/* Per stage calls from the above two functions. The void * return from /* Per stage calls from the above two functions. The void * return from
* cache_as_ram_stage_main() is the stack pointer to use in ram after * cache_as_ram_stage_main() is the stack pointer to use in RAM after
* exiting cache-as-ram mode. */ * exiting cache-as-ram mode. */
void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih); void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih);
void after_cache_as_ram_stage(void); void after_cache_as_ram_stage(void);

2
src/drivers/intel/fsp1_1/include/fsp/gma.h
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@ -52,7 +52,7 @@ typedef struct {
#define SBIOS_VERSION_SIZE 32 #define SBIOS_VERSION_SIZE 32
/* mailbox 1: public acpi methods */ /* mailbox 1: public ACPI methods */
typedef struct { typedef struct {
u32 drdy; u32 drdy;
u32 csts; u32 csts;

2
src/drivers/intel/fsp1_1/romstage.c
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@ -51,7 +51,7 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
timestamp_add_now(TS_START_ROMSTAGE); timestamp_add_now(TS_START_ROMSTAGE);
/* Load microcode before ram init */ /* Load microcode before RAM init */
if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS)) if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs(); intel_update_microcode_from_cbfs();

2
src/drivers/pc80/vga/vga.c
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@ -53,7 +53,7 @@ vga_fb_init(void)
vga_gr_write(0x07, 0x00); vga_gr_write(0x07, 0x00);
vga_gr_write(0x08, 0xFF); vga_gr_write(0x08, 0xFF);
/* o/e enable: ram enable */ /* o/e enable: RAM enable */
vga_misc_mask(0x22, 0x22); vga_misc_mask(0x22, 0x22);
} }