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mainboard/*/romstage.c: Sanitize system header inclusions

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Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.

Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Edward O'Callaghan
2015-01-04 21:33:39 +11:00
parent d76ac6349d
commit 77757c22b9
181 changed files with 682 additions and 682 deletions
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16
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@@ -34,20 +34,20 @@
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <cpu/amd/model_10xxx_rev.h>
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <lib.h>
#include "cpu/x86/lapic.h"
#include <cpu/x86/lapic.h>
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
#include <cpu/x86/bist.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71859/f71859.h>
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include "northbridge/amd/amdfam10/debug.c"
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
@@ -59,12 +59,12 @@ static int spd_read_byte(u32 device, u32 address)
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <northbridge/amd/amdfam10/amdfam10.h>
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/microcode.h"
#include <cpu/amd/microcode.h>
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"

8
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
View File

@@ -24,16 +24,16 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <southbridge/amd/cs5536/cs5536.h>
#include <spd.h>
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/amd/lx/raminit.h"
#include <northbridge/amd/lx/raminit.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)