mb/google/nissa/var/yaviks: Update devicetree setting
Update Devicetree according to yaviks's design. BUG=b:242277219 TEST=emerge-nissa coreboot Change-Id: I5d91cccbb44787bcbe7258a817ff97b6dce86c2e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
This commit is contained in:
Wisley Chen
Martin L Roth
parent
bbd07043ff
commit
77963b9d81
@ -279,3 +279,4 @@ config BOARD_GOOGLE_GAELIN4ADL
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config BOARD_GOOGLE_YAVIKS
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bool "-> Yaviks"
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select DRIVERS_GENESYSLOGIC_GL9750
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@ -1,6 +1,295 @@
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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# Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
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# Bit 2 - C1 has a redriver which does SBU muxing.
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# Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
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register "tcss_aux_ori" = "1"
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
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# Configure external V1P05/Vnn/VnnSx Rails
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
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.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
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.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
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.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
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.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
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.v1p05_voltage_mv = 1050,
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.vnn_voltage_mv = 780,
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.vnn_sx_voltage_mv = 1050,
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.v1p05_icc_max_ma = 500,
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.vnn_icc_max_ma = 500,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C1 | Touchscreen |
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#| I2C3 | Audio |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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end
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""CPU""
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register "options.tsr[1].desc" = ""5V Regulator""
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register "options.tsr[2].desc" = ""Charger""
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# TODO: below values are initial reference values only
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
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[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 6000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200
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},
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.pl2 = {
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.min_power = 25000,
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.max_power = 25000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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device generic 0 on end
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end
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end
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device ref i2c1 on
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chip drivers/i2c/hid
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register "generic.hid" = ""ELAN2513""
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register "generic.desc" = ""ELAN Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "generic.reset_delay_ms" = "20"
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register "generic.reset_off_delay_ms" = "2"
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register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
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register "generic.stop_delay_ms" = "280"
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register "generic.stop_off_delay_ms" = "2"
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register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "generic.enable_delay_ms" = "1"
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register "generic.has_power_resource" = "1"
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register "generic.disable_gpio_export_in_crs" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 10 on end
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end
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chip drivers/i2c/hid
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register "generic.hid" = ""GTCH7503""
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register "generic.desc" = ""G2TOUCH Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "generic.reset_delay_ms" = "50"
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register "generic.enable_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "generic.enable_delay_ms" = "1"
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register "generic.has_power_resource" = "1"
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register "generic.disable_gpio_export_in_crs" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 40 on end
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end
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end
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device ref i2c3 on
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chip drivers/i2c/generic
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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end
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device ref i2c5 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
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register "wake" = "GPE0_DW2_14"
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register "probed" = "1"
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device i2c 15 on end
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end
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end
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device ref hda on
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chip drivers/generic/max98357a
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register "hid" = ""MX98360A""
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register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
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register "sdmode_delay" = "5"
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device generic 0 on end
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end
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end
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device ref pcie_rp4 on
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# PCIe 4 WLAN
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register "pch_pcie_rp[PCH_RP(4)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip drivers/wifi/generic
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register "wake" = "GPE0_DW1_03"
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device pci 00.0 on end
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end
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end
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device ref emmc on
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probe STORAGE STORAGE_EMMC
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end
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device ref ish on
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probe STORAGE STORAGE_UFS
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end
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device ref ufs on
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probe STORAGE STORAGE_UFS
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end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use tcss_usb3_port2 as usb3_port
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device generic 1 alias conn1 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port2 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A1 (DB)""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
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device ref usb2_port4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 UFC""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port8 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""CNVi Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port10 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A1 (DB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
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device ref usb3_port1 on end
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end
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end
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end
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end
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end
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end
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