baytrail: SMM support
Initialize SMM on all CPUs by relocating the SMM region
and setting SMRR on all the cores. Additionally SMI
is enabled in the south cluster.
BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted rambi. Tested with DEBUG_SMI and noted
power button turns off board while in firmware.
Change-Id: I92e3460572feeb67d4a3d4d26af5f0ecaf7d3dd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173983
Reviewed-on: http://review.coreboot.org/4892
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Aaron Durbin
committed by
Aaron Durbin
Aaron Durbin
parent
6a360048a1
commit
7837be6cbb
399
src/soc/intel/baytrail/smihandler.c
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399
src/soc/intel/baytrail/smihandler.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <arch/hlt.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_def.h>
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#include <elog.h>
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#include <baytrail/pci_devs.h>
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#include <baytrail/pmc.h>
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#include <baytrail/nvs.h>
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/* GNVS needs to be set by coreboot initiating a software SMI. */
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static global_nvs_t *gnvs;
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static int smm_initialized;
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int southbridge_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x32:
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printk(BIOS_DEBUG, "OS Init\n");
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/* gnvs->smif:
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* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*/
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gnvs->smif = 0;
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return 1; /* IO trap handled */
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}
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/* Not handled */
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return 0;
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}
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void southbridge_smi_set_eos(void)
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{
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enable_smi(EOS);
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}
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global_nvs_t *smm_get_gnvs(void)
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{
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return gnvs;
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}
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static void busmaster_disable_on_bus(int bus)
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{
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int slot, func;
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unsigned int val;
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unsigned char hdr;
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for (slot = 0; slot < 0x20; slot++) {
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for (func = 0; func < 8; func++) {
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u32 reg32;
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device_t dev = PCI_DEV(bus, slot, func);
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val = pci_read_config32(dev, PCI_VENDOR_ID);
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if (val == 0xffffffff || val == 0x00000000 ||
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val == 0x0000ffff || val == 0xffff0000)
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continue;
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/* Disable Bus Mastering for this one device */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 &= ~PCI_COMMAND_MASTER;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* If this is a bridge, then follow it. */
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hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
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hdr &= 0x7f;
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if (hdr == PCI_HEADER_TYPE_BRIDGE ||
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hdr == PCI_HEADER_TYPE_CARDBUS) {
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unsigned int buses;
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buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
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busmaster_disable_on_bus((buses >> 8) & 0xff);
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}
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}
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}
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}
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static void southbridge_smi_sleep(void)
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{
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uint32_t reg32;
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uint8_t slp_typ;
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uint16_t pmbase = get_pmbase();
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/* First, disable further SMIs */
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disable_smi(SLP_SMI_EN);
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/* Figure out SLP_TYP */
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reg32 = inl(pmbase + PM1_CNT);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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slp_typ = (reg32 >> 10) & 7;
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/* Do any mainboard sleep handling */
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mainboard_smi_sleep(slp_typ-2);
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#if CONFIG_ELOG_GSMI
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/* Log S3, S4, and S5 entry */
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if (slp_typ >= 5)
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elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
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#endif
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/* Next, do the deed.
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*/
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switch (slp_typ) {
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case SLP_TYP_S0:
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printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
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break;
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case SLP_TYP_S1:
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printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
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break;
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case SLP_TYP_S3:
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printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
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/* Invalidate the cache before going to S3 */
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wbinvd();
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break;
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case SLP_TYP_S4:
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printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
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break;
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case SLP_TYP_S5:
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printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
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/* Disable all GPE */
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disable_all_gpe();
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/* also iterates over all bridges on bus 0 */
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busmaster_disable_on_bus(0);
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break;
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default:
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printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
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break;
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}
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/* Write back to the SLP register to cause the originally intended
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* event again. We need to set BIT13 (SLP_EN) though to make the
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* sleep happen.
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*/
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enable_pm1_control(SLP_EN);
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/* Make sure to stop executing code here for S3/S4/S5 */
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if (slp_typ > 1)
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hlt();
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/* In most sleep states, the code flow of this function ends at
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* the line above. However, if we entered sleep state S1 and wake
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* up again, we will continue to execute code in this function.
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*/
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reg32 = inl(pmbase + PM1_CNT);
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if (reg32 & SCI_EN) {
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/* The OS is not an ACPI OS, so we set the state to S0 */
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disable_pm1_control(SLP_EN | SLP_TYP);
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}
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}
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/*
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* Look for Synchronous IO SMI and use save state from that
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* core in case we are not running on the same core that
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* initiated the IO transaction.
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*/
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static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
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{
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em64t100_smm_state_save_area_t *state;
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int node;
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/* Check all nodes looking for the one that issued the IO */
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for (node = 0; node < CONFIG_MAX_CPUS; node++) {
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state = smm_get_save_state(node);
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/* Check for Synchronous IO (bit0==1) */
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if (!(state->io_misc_info & (1 << 0)))
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continue;
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/* Make sure it was a write (bit4==0) */
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if (state->io_misc_info & (1 << 4))
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continue;
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/* Check for APMC IO port */
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if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
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continue;
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/* Check AX against the requested command */
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if ((state->rax & 0xff) != cmd)
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continue;
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return state;
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}
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return NULL;
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}
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#if CONFIG_ELOG_GSMI
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static void southbridge_smi_gsmi(void)
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{
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u32 *ret, *param;
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uint8_t sub_command;
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em64t100_smm_state_save_area_t *io_smi =
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smi_apmc_find_state_save(ELOG_GSMI_APM_CNT);
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if (!io_smi)
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return;
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/* Command and return value in EAX */
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ret = (u32*)&io_smi->rax;
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sub_command = (uint8_t)(*ret >> 8);
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/* Parameter buffer in EBX */
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param = (u32*)&io_smi->rbx;
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/* drivers/elog/gsmi.c */
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*ret = gsmi_exec(sub_command, param);
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}
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#endif
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static void southbridge_smi_apmc(void)
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{
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uint8_t reg8;
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em64t100_smm_state_save_area_t *state;
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/* Emulate B2 register as the FADT / Linux expects it */
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reg8 = inb(APM_CNT);
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switch (reg8) {
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case APM_CNT_CST_CONTROL:
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/* Calling this function seems to cause
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* some kind of race condition in Linux
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* and causes a kernel oops
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*/
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printk(BIOS_DEBUG, "C-state control\n");
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break;
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case APM_CNT_PST_CONTROL:
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/* Calling this function seems to cause
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* some kind of race condition in Linux
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* and causes a kernel oops
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*/
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printk(BIOS_DEBUG, "P-state control\n");
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break;
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case APM_CNT_ACPI_DISABLE:
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disable_pm1_control(SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
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break;
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case APM_CNT_ACPI_ENABLE:
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enable_pm1_control(SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
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break;
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case APM_CNT_GNVS_UPDATE:
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if (smm_initialized) {
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printk(BIOS_DEBUG,
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"SMI#: SMM structures already initialized!\n");
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return;
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}
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state = smi_apmc_find_state_save(reg8);
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if (state) {
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/* EBX in the state save contains the GNVS pointer */
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gnvs = (global_nvs_t *)((uint32_t)state->rbx);
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smm_initialized = 1;
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printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
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}
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break;
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#if CONFIG_ELOG_GSMI
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case ELOG_GSMI_APM_CNT:
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southbridge_smi_gsmi();
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break;
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#endif
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}
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mainboard_smi_apmc(reg8);
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}
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static void southbridge_smi_pm1(void)
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{
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uint16_t pm1_sts = clear_pm1_status();
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/* While OSPM is not active, poweroff immediately
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* on a power button event.
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*/
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if (pm1_sts & PWRBTN_STS) {
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// power button pressed
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#if CONFIG_ELOG_GSMI
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elog_add_event(ELOG_TYPE_POWER_BUTTON);
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#endif
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disable_pm1_control(-1UL);
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enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
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}
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}
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static void southbridge_smi_gpe0(void)
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{
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clear_gpe_status();
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}
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static void southbridge_smi_tco(void)
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{
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uint32_t tco_sts = clear_tco_status();
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/* Any TCO event? */
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if (!tco_sts)
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return;
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if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */
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/* Handle TCO timeout */
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printk(BIOS_DEBUG, "TCO Timeout.\n");
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}
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}
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static void southbridge_smi_periodic(void)
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{
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uint32_t reg32;
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reg32 = inl(get_pmbase() + SMI_EN);
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/* Are periodic SMIs enabled? */
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if ((reg32 & PERIODIC_EN) == 0)
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return;
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printk(BIOS_DEBUG, "Periodic SMI.\n");
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}
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typedef void (*smi_handler_t)(void);
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static const smi_handler_t southbridge_smi[32] = {
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NULL, // [0] reserved
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NULL, // [1] reserved
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NULL, // [2] BIOS_STS
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NULL, // [3] LEGACY_USB_STS
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southbridge_smi_sleep, // [4] SLP_SMI_STS
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southbridge_smi_apmc, // [5] APM_STS
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NULL, // [6] SWSMI_TMR_STS
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NULL, // [7] reserved
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southbridge_smi_pm1, // [8] PM1_STS
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southbridge_smi_gpe0, // [9] GPE0_STS
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NULL, // [10] reserved
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NULL, // [11] reserved
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NULL, // [12] reserved
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southbridge_smi_tco, // [13] TCO_STS
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southbridge_smi_periodic, // [14] PERIODIC_STS
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NULL, // [15] SERIRQ_SMI_STS
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NULL, // [16] SMBUS_SMI_STS
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NULL, // [17] LEGACY_USB2_STS
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NULL, // [18] INTEL_USB2_STS
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NULL, // [19] reserved
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NULL, // [20] PCI_EXP_SMI_STS
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NULL, // [21] reserved
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NULL, // [22] reserved
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NULL, // [23] reserved
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NULL, // [24] reserved
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NULL, // [25] reserved
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NULL, // [26] SPI_STS
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NULL, // [27] reserved
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NULL, // [28] PUNIT
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NULL, // [29] GUNIT
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NULL, // [30] reserved
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NULL // [31] reserved
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};
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void southbridge_smi_handler(void)
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{
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int i;
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uint32_t smi_sts;
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/* We need to clear the SMI status registers, or we won't see what's
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* happening in the following calls.
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*/
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smi_sts = clear_smi_status();
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/* Call SMI sub handler for each of the status bits */
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for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
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if (!(smi_sts & (1 << i)))
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continue;
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if (southbridge_smi[i] != NULL) {
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southbridge_smi[i]();
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} else {
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printk(BIOS_DEBUG,
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"SMI_STS[%d] occured, but no "
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"handler available.\n", i);
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}
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}
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}
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