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soc/intel/common/block: Move p2sb common functions into block/p2sb

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This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/p2sb.

BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.

Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik
2018-05-07 17:13:40 +05:30
parent 210b351df3
commit 7837c203d6
16 changed files with 276 additions and 134 deletions
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46
src/soc/intel/skylake/p2sb.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <intelblocks/p2sb.h>
void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
{
uint32_t mask;
if (count != P2SB_EP_MASK_MAX_REG) {
printk(BIOS_ERR, "Unable to program EPMASK registers\n");
return;
}
/*
* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband
* access for PCI Root Bridge.
* Set p2sb PCI offset EPMASK5 [17, 16,10, 1] to disable Sideband
* access for MIPI controller.
*/
mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26) | (1 << 17) |
(1 << 16) | (1 << 10) | (1 << 1);
ep_mask[P2SB_EP_MASK_5_REG] = mask;
/*
* Set p2sb PCI offset EPMASK7 [6, 5] to disable Sideband
* access for XHCI controller.
*/
mask = (1 << 6) | (1 << 5);
ep_mask[P2SB_EP_MASK_7_REG] = mask;
}