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sb/intel/bd82x6x/acpi: Convert to ASL 2.0

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Change-Id: Ib587d7a982852e7123e43337407ef20d96811719
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Elyes HAOUAS 2021-02-05 20:13:21 +01:00 committed by Michael Niewöhner
parent 93329d8189
commit 78452a584a
2 changed files with 53 additions and 53 deletions
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46
src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
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@ -111,53 +111,53 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Set flag to enable USB charging in S3 */ /* Set flag to enable USB charging in S3 */
Method (S3UE) Method (S3UE)
{ {
Store (One, \S3U0) \S3U0 = 1
Store (One, \S3U1) \S3U1 = 1
} }
/* Set flag to disable USB charging in S3 */ /* Set flag to disable USB charging in S3 */
Method (S3UD) Method (S3UD)
{ {
Store (Zero, \S3U0) \S3U0 = 0
Store (Zero, \S3U1) \S3U1 = 0
} }
/* Set flag to enable USB charging in S5 */ /* Set flag to enable USB charging in S5 */
Method (S5UE) Method (S5UE)
{ {
Store (One, \S5U0) \S5U0 = 1
Store (One, \S5U1) \S5U1 = 1
} }
/* Set flag to disable USB charging in S5 */ /* Set flag to disable USB charging in S5 */
Method (S5UD) Method (S5UD)
{ {
Store (Zero, \S5U0) \S5U0 = 0
Store (Zero, \S5U1) \S5U1 = 0
} }
/* Set flag to enable 3G module in S3 */ /* Set flag to enable 3G module in S3 */
Method (S3GE) Method (S3GE)
{ {
Store (One, \S33G) \S33G = 1
} }
/* Set flag to disable 3G module in S3 */ /* Set flag to disable 3G module in S3 */
Method (S3GD) Method (S3GD)
{ {
Store (Zero, \S33G) \S33G = 0
} }
/* Set XHCI Mode enable */ /* Set XHCI Mode enable */
Method (XHCE) Method (XHCE)
{ {
Store (One, \XHCI) \XHCI = 1
} }
/* Set XHCI Mode disable */ /* Set XHCI Mode disable */
Method (XHCD) Method (XHCD)
{ {
Store (Zero, \XHCI) \XHCI = 0
} }
External (\_TZ.SKIN) External (\_TZ.SKIN)
@ -179,46 +179,46 @@ Method (TZUP)
/* Update Fan 0 thresholds */ /* Update Fan 0 thresholds */
Method (F0UT, 2) Method (F0UT, 2)
{ {
Store (Arg0, \F0OF) \F0OF = Arg0
Store (Arg1, \F0ON) \F0ON = Arg1
TZUP () TZUP ()
} }
/* Update Fan 1 thresholds */ /* Update Fan 1 thresholds */
Method (F1UT, 2) Method (F1UT, 2)
{ {
Store (Arg0, \F1OF) \F1OF = Arg0
Store (Arg1, \F1ON) \F1ON = Arg1
TZUP () TZUP ()
} }
/* Update Fan 2 thresholds */ /* Update Fan 2 thresholds */
Method (F2UT, 2) Method (F2UT, 2)
{ {
Store (Arg0, \F2OF) \F2OF = Arg0
Store (Arg1, \F2ON) \F2ON = Arg1
TZUP () TZUP ()
} }
/* Update Fan 3 thresholds */ /* Update Fan 3 thresholds */
Method (F3UT, 2) Method (F3UT, 2)
{ {
Store (Arg0, \F3OF) \F3OF = Arg0
Store (Arg1, \F3ON) \F3ON = Arg1
TZUP () TZUP ()
} }
/* Update Fan 4 thresholds */ /* Update Fan 4 thresholds */
Method (F4UT, 2) Method (F4UT, 2)
{ {
Store (Arg0, \F4OF) \F4OF = Arg0
Store (Arg1, \F4ON) \F4ON = Arg1
TZUP () TZUP ()
} }
/* Update Temperature Sensor ID */ /* Update Temperature Sensor ID */
Method (TMPU, 1) Method (TMPU, 1)
{ {
Store (Arg0, \TMPS) \TMPS = Arg0
TZUP () TZUP ()
} }

60
src/southbridge/intel/bd82x6x/acpi/usb.asl
View File

@ -37,12 +37,12 @@ Device (EHC1)
}) })
// REV: Revision 0x02 for ACPI 5.0 // REV: Revision 0x02 for ACPI 5.0
CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) CreateField (DerefOf (PCKG [0]), 0, 0x07, REV)
Store (0x02, REV) REV = 0x02
// VISI: Port visibility to user per port // VISI: Port visibility to user per port
CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI)
Store (Arg0, VISI) VISI = Arg0
Return (PCKG) Return (PCKG)
} }
@ -90,12 +90,12 @@ Device (EHC2)
}) })
// REV: Revision 0x02 for ACPI 5.0 // REV: Revision 0x02 for ACPI 5.0
CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) CreateField (DerefOf (PCKG [0]), 0, 0x07, REV)
Store (0x02, REV) REV = 0x02
// VISI: Port visibility to user per port // VISI: Port visibility to user per port
CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI)
Store (Arg0, VISI) VISI = Arg0
Return (PCKG) Return (PCKG)
} }
@ -137,38 +137,38 @@ Device (XHC)
CreateDWordField(Arg1,0,CDW1) CreateDWordField(Arg1,0,CDW1)
// Check revision // Check revision
If(LNotEqual(Arg0,One)) { If(Arg0 != 1) {
// Set unknown revision bit // Set unknown revision bit
Or(CDW1,0x8,CDW1) CDW1 |= 8
} }
// Set failure if xHCI is disabled by coreboot // Set failure if xHCI is disabled by coreboot
If(LEqual(XHCI, 0)) { If(XHCI == 0) {
Or(CDW1,0x2,CDW1) CDW1 |= 2
} }
// Query flag clear and xHCI in auto mode // Query flag clear and xHCI in auto mode
If(LAnd(LNot(And(CDW1,0x1)),LOr(LEqual(XHCI ,2), LEqual(XHCI ,3)))) { If(!(CDW1 & 0x1) && (XHCI == 2 || XHCI == 3)) {
Store ("XHCI Switch", Debug) Debug = "XHCI Switch"
Store(Zero, Local0) Local0 = 0
And(XPRT, 0x3, Local0) Local0 = XPRT & 0x03
If(LOr(LEqual(Local0, 0), LEqual(Local0, 1))) { If(Local0 == 0 || Local0 == 1) {
Store(0xF, Local1) Local1 = 0x0f
} }
ElseIf(LEqual(Local0, 2)) { ElseIf(Local0 == 2) {
Store(0x3, Local1) Local1 = 3
} }
ElseIf(LEqual(Local0, 3)) { ElseIf(Local0 == 3) {
Store(Zero, Local1) Local1 = 0
} }
And(RPM3, 0xFFFFFFF0, Local0) Local0 = RPM3 & 0xfffffff0
Or(Local0, Local1, RPM3) RPM3 = Local0 | Local1
And(PRM2, 0xFFFFFFF0, Local0) Local0 = PRM2 & 0xfffffff0
Or(Local0, Local1, PRM2) PRM2 = Local0 | Local1
And(SSEN, 0xFFFFFFF0, Local0) Local0 = SSEN & 0xfffffff0
Or(Local0, Local1, SSEN) SSEN = Local0 | Local1
And(X2PR, 0xFFFFFFF0, Local0) Local0 = X2PR & 0xfffffff0
Or(Local0, Local1, X2PR) X2PR = Local0 | Local1
} }
Return(Arg1) Return(Arg1)
} }