Remove XIP_ROM_BASE

The base is now calculated automatically, and all mentions of that config option were typical anyway (4GB - XIP_ROM_SIZE). Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/366 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-31 17:07:52 +01:00
parent 36c04e8a5c
commit 784544b934
17 changed files with 12 additions and 70 deletions
--- a/src/cpu/amd/agesa/family10/Kconfig
+++ b/src/cpu/amd/agesa/family10/Kconfig
@@ -40,10 +40,6 @@ config CDB
 	hex
 	default 0x18

-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000
--- a/src/cpu/amd/agesa/family12/Kconfig
+++ b/src/cpu/amd/agesa/family12/Kconfig
@@ -57,11 +57,6 @@ config CDB
 	default 0x18
 	depends on CPU_AMD_AGESA_FAMILY12

-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_AGESA_FAMILY12
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000
--- a/src/cpu/amd/agesa/family14/Kconfig
+++ b/src/cpu/amd/agesa/family14/Kconfig
@@ -57,11 +57,6 @@ config CDB
 	default 0x18
 	depends on CPU_AMD_AGESA_FAMILY14

-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_AGESA_FAMILY14
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -279,7 +279,7 @@ clear_fixed_var_mtrr_out:
 	movl	$(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
 	wrmsr

-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE

 	/* Enable write base caching so we can do execute in place (XIP)
 	 * on the flash ROM.
@@ -302,7 +302,7 @@ clear_fixed_var_mtrr_out:
 wbcache_post_fam10_setup:
 	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */

 	/* Set the default memory type and enable fixed and variable MTRRs. */
 	movl	$MTRRdefType_MSR, %ecx
--- a/src/cpu/amd/socket_AM2r2/Kconfig
+++ b/src/cpu/amd/socket_AM2r2/Kconfig
@@ -30,11 +30,6 @@ config CDB
 	default 0x18
 	depends on CPU_AMD_SOCKET_AM2R2

-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_SOCKET_AM2R2
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000
--- a/src/cpu/amd/socket_AM3/Kconfig
+++ b/src/cpu/amd/socket_AM3/Kconfig
@@ -30,11 +30,6 @@ config CDB
 	default 0x18
 	depends on CPU_AMD_SOCKET_AM3

-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_SOCKET_AM3
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000
--- a/src/cpu/amd/socket_ASB2/Kconfig
+++ b/src/cpu/amd/socket_ASB2/Kconfig
@@ -30,11 +30,6 @@ config CDB
 	default 0x18
 	depends on CPU_AMD_SOCKET_ASB2

-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_SOCKET_ASB2
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000
--- a/src/cpu/amd/socket_C32/Kconfig
+++ b/src/cpu/amd/socket_C32/Kconfig
@@ -30,11 +30,6 @@ config CDB
 	default 0x18
 	depends on CPU_AMD_SOCKET_C32

-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_SOCKET_C32
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000
--- a/src/cpu/amd/socket_F_1207/Kconfig
+++ b/src/cpu/amd/socket_F_1207/Kconfig
@@ -29,11 +29,6 @@ config CDB
 	default 0x18
 	depends on CPU_AMD_SOCKET_F_1207

-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-	depends on CPU_AMD_SOCKET_F_1207
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000