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Remove remaining uses of

Browse Source 
HAVE_FAILOVER_BOOT
HAVE_FALLBACK_BOOT
USE_FAILOVER_IMAGE
USE_FALLBACK_IMAGE

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi
2010-03-18 20:58:41 +00:00
parent 2bd9100341
commit 78acf93291
42 changed files with 0 additions and 385 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
src/cpu/amd/car/cache_as_ram.inc
View File

@ -71,9 +71,6 @@ cache_as_ram_setup:
cvtsi2sd %eax, %xmm2
cvtsd2si %xmm3, %ebx
/* hope we can skip the double set for normal part */
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* check if cpu_init_detected */
movl $MTRRdefType_MSR, %ecx
rdmsr
@ -248,15 +245,6 @@ clear_fixed_var_mtrr_out:
xorl %edx, %edx
movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
#endif /* CONFIG_USE_FAILOVER_IMAGE == 1*/
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
/* disable cache */
movl %cr0, %eax
orl $(0x1 << 30), %eax
movl %eax, %cr0
#endif
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* enable write base caching so we can do execute in place
@ -283,7 +271,6 @@ wbcache_post_fam10_setup:
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
@ -296,7 +283,6 @@ wbcache_post_fam10_setup:
rdmsr
orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
wrmsr
#endif
movb $0xA1, %al
outb %al, $0x80
@ -318,7 +304,6 @@ fam10_end_part1:
movb $0xA2, %al
outb %al, $0x80
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* Read the range with lodsl*/
cld
movl $CacheBase, %esi
@ -331,8 +316,6 @@ fam10_end_part1:
xorl %eax, %eax
rep stosl
#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
/* set up the stack pointer */
movl $(CacheBase + CacheSize - GlobalVarSize), %eax
movl %eax, %esp

3
src/cpu/intel/model_106cx/cache_as_ram.inc
View File

@ -29,8 +29,6 @@
movl %eax, %ebp
cache_as_ram:
#if CONFIG_USE_FALLBACK_IMAGE == 1
post_code(0x20)
/* Send INIT IPI to all excluding ourself */
@ -134,7 +132,6 @@ clear_mtrrs:
movl %cr0, %eax
andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
movl %eax, %cr0
#endif
/* Set up stack pointer */
#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)

3
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -29,8 +29,6 @@
movl %eax, %ebp
cache_as_ram:
#if CONFIG_USE_FALLBACK_IMAGE == 1
post_code(0x20)
/* Send INIT IPI to all excluding ourself */
@ -123,7 +121,6 @@ clear_mtrrs:
movl %cr0, %eax
andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
movl %eax, %cr0
#endif
/* Set up stack pointer */
#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)

3
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -29,8 +29,6 @@
movl %eax, %ebp
cache_as_ram:
#if CONFIG_USE_FALLBACK_IMAGE == 1
post_code(0x20)
/* Send INIT IPI to all excluding ourself */
@ -130,7 +128,6 @@ clear_mtrrs:
movl %cr0, %eax
andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
movl %eax, %cr0
#endif
/* Set up stack pointer */
#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)

17
src/cpu/x86/car/cache_as_ram.inc
View File

@ -36,9 +36,6 @@
movl %eax, %ebp
CacheAsRam:
/* hope we can skip the double set for normal part */
#if CONFIG_USE_FALLBACK_IMAGE == 1
// Check whether the processor has HT capability
movl $01, %eax
cpuid
@ -191,14 +188,6 @@ clear_fixed_var_mtrr_out:
simplemask CacheSize, 0
wrmsr
#else
/* disable cache */
movl %cr0, %eax
orl $(0x1 << 30), %eax
movl %eax, %cr0
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
@ -225,8 +214,6 @@ clear_fixed_var_mtrr_out:
andl $0x9fffffff, %eax
movl %eax, %cr0
#if CONFIG_USE_FALLBACK_IMAGE == 1
/* Read the range with lodsl*/
movl $CacheBase, %esi
cld
@ -283,8 +270,6 @@ clear_fixed_var_mtrr_out:
.xout1x:
#endif
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
movl $(CacheBase + CacheSize - 4), %eax
movl %eax, %esp
@ -319,7 +304,6 @@ var_mtrr_msr:
.long 0x20C, 0x20D, 0x20E, 0x20F
.long 0x000 /* NULL, end of table */
#if CONFIG_USE_FALLBACK_IMAGE == 1
.align 0x1000
.code16
.global LogicalAP_SIPI
@ -349,5 +333,4 @@ Halt_LogicalAP:
hlt
jmp Halt_LogicalAP
.code32
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
.CacheAsRam_out: