Remove remaining uses of
HAVE_FAILOVER_BOOT HAVE_FALLBACK_BOOT USE_FAILOVER_IMAGE USE_FALLBACK_IMAGE Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -36,9 +36,6 @@
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movl %eax, %ebp
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CacheAsRam:
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/* hope we can skip the double set for normal part */
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#if CONFIG_USE_FALLBACK_IMAGE == 1
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// Check whether the processor has HT capability
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movl $01, %eax
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cpuid
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@@ -191,14 +188,6 @@ clear_fixed_var_mtrr_out:
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simplemask CacheSize, 0
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wrmsr
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#else
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/* disable cache */
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movl %cr0, %eax
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orl $(0x1 << 30), %eax
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movl %eax, %cr0
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#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/
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#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
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#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
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#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
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@@ -225,8 +214,6 @@ clear_fixed_var_mtrr_out:
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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#if CONFIG_USE_FALLBACK_IMAGE == 1
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/* Read the range with lodsl*/
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movl $CacheBase, %esi
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cld
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@@ -283,8 +270,6 @@ clear_fixed_var_mtrr_out:
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.xout1x:
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#endif
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#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
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movl $(CacheBase + CacheSize - 4), %eax
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movl %eax, %esp
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@@ -319,7 +304,6 @@ var_mtrr_msr:
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.long 0x20C, 0x20D, 0x20E, 0x20F
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.long 0x000 /* NULL, end of table */
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#if CONFIG_USE_FALLBACK_IMAGE == 1
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.align 0x1000
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.code16
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.global LogicalAP_SIPI
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@@ -349,5 +333,4 @@ Halt_LogicalAP:
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hlt
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jmp Halt_LogicalAP
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.code32
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#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
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.CacheAsRam_out:
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