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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-03-17 22:09:26 +00:00
committed by Stefan Reinauer
parent 527aedc17b
commit 78b4033584
11 changed files with 65 additions and 77 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
src/southbridge/amd/cs5536/cs5536.c
View File

@@ -35,7 +35,7 @@
#include "cs5536.h"
struct msrinit {
uint32_t msrnum;
u32 msrnum;
msr_t msr;
};
@@ -61,8 +61,8 @@ struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
};
struct acpiinit {
uint16_t ioreg;
uint32_t regdata;
u16 ioreg;
u32 regdata;
};
struct acpiinit acpi_init_table[] = {
@@ -95,7 +95,7 @@ struct FLASH_DEVICE FlashInitTable[] = {
#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
uint32_t FlashPort[] = {
u32 FlashPort[] = {
MDD_LBAR_FLSH0,
MDD_LBAR_FLSH1,
MDD_LBAR_FLSH2,
@@ -111,8 +111,8 @@ uint32_t FlashPort[] = {
/* ***************************************************************************/
static void pmChipsetInit(void)
{
uint32_t val = 0;
uint16_t port;
u32 val = 0;
u16 port;
port = (PMS_IO_BASE + 0x010);
val = 0x0E00; /* 1ms */
@@ -427,7 +427,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
{
uint8_t *bar;
u32 bar;
msr_t msr;
device_t dev;
@@ -443,7 +443,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
/* write to clear diag register */
wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
/* Make HCCPARAMS writeable */
write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
@@ -455,7 +455,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);
@@ -483,8 +483,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
bar = (uint8_t *) pci_read_config32(dev,
PCI_BASE_ADDRESS_0);
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
write32(bar + UDCDEVCTL,
read32(bar + UDCDEVCTL) | UDC_SD_SET);
@@ -493,8 +492,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
bar = (uint8_t *) pci_read_config32(dev,
PCI_BASE_ADDRESS_0);
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);
write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);
}
@@ -524,7 +522,7 @@ void chipsetinit(void)
{
device_t dev;
msr_t msr;
uint32_t msrnum;
u32 msrnum;
struct southbridge_amd_cs5536_config *sb =
(struct southbridge_amd_cs5536_config *)dev->chip_info;
struct msrinit *csi;

12
src/southbridge/amd/cs5536/cs5536_early_setup.c
View File

@@ -32,13 +32,11 @@ static void cs5536_setup_extmsr(void)
/* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
msr.hi = msr.lo = 0x00000000;
if (CS5536_GLINK_PORT_NUM <= 4) {
msr.lo = CS5536_DEV_NUM <<
(unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
} else {
msr.hi = CS5536_DEV_NUM <<
(unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
}
#if CS5536_GLINK_PORT_NUM <= 4
msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
#else
msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
#endif
wrmsr(GLPCI_ExtMSR, msr);
}

18
src/southbridge/amd/sb600/sb600_hda.c
View File

@@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
static int set_bits(u8 * port, u32 mask, u32 val)
static int set_bits(u32 port, u32 mask, u32 val)
{
u32 dword;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u8 * port, u32 mask, u32 val)
return 0;
}
static u32 codec_detect(u8 * base)
static u32 codec_detect(u32 base)
{
u32 dword;
@@ -172,7 +172,7 @@ static u32 find_verb(u32 viddid, u32 ** verb)
* no response would imply that the codec is non-operative
*/
static int wait_for_ready(u8 *base)
static int wait_for_ready(u32 base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -195,7 +195,7 @@ static int wait_for_ready(u8 *base)
* is non-operative
*/
static int wait_for_valid(u8 *base)
static int wait_for_valid(u32 base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -212,7 +212,7 @@ static int wait_for_valid(u8 *base)
return 1;
}
static void codec_init(u8 * base, int addr)
static void codec_init(u32 base, int addr)
{
u32 dword;
u32 *verb;
@@ -254,7 +254,7 @@ static void codec_init(u8 * base, int addr)
printk_debug("verb loaded!\n");
}
static void codecs_init(u8 * base, u32 codec_mask)
static void codecs_init(u32 base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -267,7 +267,7 @@ static void hda_init(struct device *dev)
{
u8 byte;
u32 dword;
u8 *base;
u32 base;
struct resource *res;
u32 codec_mask;
device_t sm_dev;
@@ -301,8 +301,8 @@ static void hda_init(struct device *dev)
if (!res)
return;
base = (u8 *) ((u32)res->base);
printk_debug("base = %p\n", base);
base = ((u32)res->base);
printk_debug("base = 0x%x\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {

8
src/southbridge/amd/sb600/sb600_sata.c
View File

@@ -27,7 +27,7 @@
#include <arch/io.h>
#include "sb600.h"
int sata_drive_detect(int portnum, u16 iobar)
static int sata_drive_detect(int portnum, u16 iobar)
{
u8 byte, byte2;
int i = 0;
@@ -59,7 +59,7 @@ static void sata_init(struct device *dev)
u8 byte;
u16 word;
u32 dword;
u8 *sata_bar5;
u32 sata_bar5;
u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
int i, j;
@@ -84,7 +84,7 @@ static void sata_init(struct device *dev)
pci_write_config8(sm_dev, 0xaf, byte);
/* get base addresss */
sata_bar5 = (u8 *) (pci_read_config32(dev, 0x24) & ~0x3FF);
sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -96,7 +96,7 @@ static void sata_init(struct device *dev)
printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */
printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */
printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */
printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */
printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */
/* Program the 2C to 0x43801002 */
dword = 0x43801002;

6
src/southbridge/amd/sb600/sb600_usb.c
View File

@@ -88,13 +88,13 @@ static void usb_init2(struct device *dev)
u8 byte;
u16 word;
u32 dword;
u8 *usb2_bar0;
u32 usb2_bar0;
/* dword = pci_read_config32(dev, 0xf8); */
/* dword |= 40; */
/* pci_write_config32(dev, 0xf8, dword); */
usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF);
printk_info("usb2_bar0=%p\n", usb2_bar0);
usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
printk_info("usb2_bar0=0x%x\n", usb2_bar0);
/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
dword = 0x00020F00;

18
src/southbridge/amd/sb700/sb700_hda.c
View File

@@ -30,7 +30,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
static int set_bits(u8 * port, u32 mask, u32 val)
static int set_bits(u32 port, u32 mask, u32 val)
{
u32 dword;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u8 * port, u32 mask, u32 val)
return 0;
}
static u32 codec_detect(u8 * base)
static u32 codec_detect(u32 base)
{
u32 dword;
@@ -94,7 +94,7 @@ no_codec:
* Wait 50usec for for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
static int wait_for_ready(u8 *base)
static int wait_for_ready(u32 base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -116,7 +116,7 @@ static int wait_for_ready(u8 *base)
* the previous command. No response would imply that the code
* is non-operative
*/
static int wait_for_valid(u8 *base)
static int wait_for_valid(u32 base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -133,7 +133,7 @@ static int wait_for_valid(u8 *base)
return 1;
}
static void codec_init(u8 * base, int addr)
static void codec_init(u32 base, int addr)
{
u32 dword;
@@ -153,7 +153,7 @@ static void codec_init(u8 * base, int addr)
printk_debug("%x(th) codec viddid: %08x\n", addr, dword);
}
static void codecs_init(u8 * base, u32 codec_mask)
static void codecs_init(u32 base, u32 codec_mask)
{
int i;
for (i = 2; i >= 0; i--) {
@@ -166,7 +166,7 @@ static void hda_init(struct device *dev)
{
u8 byte;
u32 dword;
u8 *base;
u32 base;
struct resource *res;
u32 codec_mask;
device_t sm_dev;
@@ -202,8 +202,8 @@ static void hda_init(struct device *dev)
if (!res)
return;
base = (u8 *) ((u32)res->base);
printk_debug("base = %p\n", base);
base = (u32)res->base;
printk_debug("base = 0x%x\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {

12
src/southbridge/amd/sb700/sb700_usb.c
View File

@@ -34,7 +34,6 @@ static void usb_init(struct device *dev)
{
u8 byte;
u16 word;
u32 dword;
/* 6.1 Enable OHCI0-4 and EHCI Controllers */
device_t sm_dev;
@@ -70,10 +69,8 @@ static void usb_init(struct device *dev)
static void usb_init2(struct device *dev)
{
u8 byte;
u16 word;
u32 dword;
u8 *usb2_bar0;
u32 usb2_bar0;
device_t sm_dev;
u8 rev;
@@ -84,8 +81,8 @@ static void usb_init2(struct device *dev)
/* dword |= 40; */
/* pci_write_config32(dev, 0xf8, dword); */
usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF);
printk_info("usb2_bar0=%p\n", usb2_bar0);
usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
printk_info("usb2_bar0=0x%x\n", usb2_bar0);
/* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
dword = 0x00020F00;
@@ -123,6 +120,9 @@ static void usb_init2(struct device *dev)
/* Each step below causes the linux crashes. Leave them here
* for future debugging. */
#if 0
u8 byte;
u16 word;
/* RPR6.16 Disable EHCI MSI support */
byte = pci_read_config8(dev, 0x50);
byte |= (1 << 6);