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soc/intel/alderlake: Add support for ADL-N PCH

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Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to
specify the correct amount of PCIe I/O.

Document number 645550 indicates that Alder Lake-N has 12 PCH root ports
and no CPU root ports.

Document number 645548 indicates ADL-N has 5 clock sources and 5 clock
request signals.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Usha P
2021-11-30 11:27:38 +05:30
committed by Tim Wawrzynczak
parent 7e7cc1a8c9
commit 78c9b678d7
2 changed files with 11 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/soc/intel/alderlake/Kconfig
View File

@@ -11,6 +11,12 @@ config SOC_INTEL_ALDERLAKE_PCH_M
help help
Choose this option if your mainboard has a PCH-M chipset. Choose this option if your mainboard has a PCH-M chipset.
config SOC_INTEL_ALDERLAKE_PCH_N
bool
select SOC_INTEL_ALDERLAKE
help
Choose this option if your mainboard has a PCH-N chipset.
config SOC_INTEL_ALDERLAKE_PCH_P config SOC_INTEL_ALDERLAKE_PCH_P
bool bool
select SOC_INTEL_ALDERLAKE select SOC_INTEL_ALDERLAKE
@@ -178,11 +184,13 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config MAX_PCH_ROOT_PORTS config MAX_PCH_ROOT_PORTS
int int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 10 if SOC_INTEL_ALDERLAKE_PCH_M
default 12 if SOC_INTEL_ALDERLAKE_PCH_N
default 12 if SOC_INTEL_ALDERLAKE_PCH_P default 12 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_CPU_ROOT_PORTS config MAX_CPU_ROOT_PORTS
int int
default 1 if SOC_INTEL_ALDERLAKE_PCH_M default 1 if SOC_INTEL_ALDERLAKE_PCH_M
default 0 if SOC_INTEL_ALDERLAKE_PCH_N
default 3 if SOC_INTEL_ALDERLAKE_PCH_P default 3 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_ROOT_PORTS config MAX_ROOT_PORTS
@@ -192,11 +200,13 @@ config MAX_ROOT_PORTS
config MAX_PCIE_CLOCK_SRC config MAX_PCIE_CLOCK_SRC
int int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 7 if SOC_INTEL_ALDERLAKE_PCH_P default 7 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_PCIE_CLOCK_REQ config MAX_PCIE_CLOCK_REQ
int int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 10 if SOC_INTEL_ALDERLAKE_PCH_P default 10 if SOC_INTEL_ALDERLAKE_PCH_P
config SMM_TSEG_SIZE config SMM_TSEG_SIZE

1
src/soc/intel/alderlake/include/soc/bootblock.h
View File

@@ -4,6 +4,7 @@
#define _SOC_ALDERLAKE_BOOTBLOCK_H_ #define _SOC_ALDERLAKE_BOOTBLOCK_H_
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \ #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \
CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + \
CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1 CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1
#error "Please select exactly one PCH type" #error "Please select exactly one PCH type"
#endif #endif