soc/amd/common/acpi/cpu_power_state: introduce & use get_pstate_latency

On the Zen-based CPUs, the transition and bus master latency are always
written as 0, but on but on Stoneyridge hardware-dependent values are
used. Introduce get_pstate_latency that returns 0 for all non-CAR AMD
CPUs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81086fa64909c7350b3b171ea6ea9b46f1708f67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

src/soc/amd/common/block/acpi/cpu_power_state.c

@@ -59,11 +59,12 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
 {
 	union pstate_msr pstate_reg;
 	size_t pstate_count, pstate;
-	uint32_t pstate_0_reg, max_pstate;
+	uint32_t pstate_0_reg, max_pstate, latency;
 
 	pstate_count = 0;
 	pstate_0_reg = get_pstate_0_reg();
 	max_pstate = get_visible_pstate_count();
+	latency = get_pstate_latency();
 
 	for (pstate = 0; pstate <= max_pstate; pstate++) {
 		pstate_reg.raw = rdmsr(PSTATE_MSR(pstate_0_reg + pstate)).raw;
@@ -73,8 +74,8 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
 
 		pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_reg);
 		pstate_values[pstate_count].power = get_pstate_core_power(pstate_reg);
-		pstate_values[pstate_count].transition_latency = 0;
-		pstate_values[pstate_count].bus_master_latency = 0;
+		pstate_values[pstate_count].transition_latency = latency;
+		pstate_values[pstate_count].bus_master_latency = latency;
 		pstate_values[pstate_count].control_value = pstate;
 		pstate_values[pstate_count].status_value = pstate;
 
@@ -82,8 +83,8 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
 			(uint64_t)pstate_values[pstate_count].core_freq;
 		pstate_xpss_values[pstate_count].power =
 			(uint64_t)pstate_values[pstate_count].power;
-		pstate_xpss_values[pstate_count].transition_latency = 0;
-		pstate_xpss_values[pstate_count].bus_master_latency = 0;
+		pstate_xpss_values[pstate_count].transition_latency = latency;
+		pstate_xpss_values[pstate_count].bus_master_latency = latency;
 		pstate_xpss_values[pstate_count].control_value = (uint64_t)pstate;
 		pstate_xpss_values[pstate_count].status_value = (uint64_t)pstate;
 		pstate_count++;

src/soc/amd/common/block/cpu/noncar/cpu.c

@@ -12,6 +12,11 @@ uint32_t get_pstate_0_reg(void)
 	return 0;
 }
 
+uint32_t get_pstate_latency(void)
+{
+	return 0;
+}
+
 unsigned int smbios_processor_family(struct cpuid_result res)
 {
 	return 0x6b; /* Zen */

src/soc/amd/common/block/include/amdblocks/cpu.h

@@ -18,6 +18,7 @@ union pstate_msr; /* proper definition is in soc/msr.h */
 
 uint32_t get_uvolts_from_vid(uint16_t core_vid);
 uint32_t get_pstate_0_reg(void);
+uint32_t get_pstate_latency(void);
 uint32_t get_pstate_core_freq(union pstate_msr pstate_reg);
 uint32_t get_pstate_core_uvolts(union pstate_msr pstate_reg);
 const acpi_cstate_t *get_cstate_config_data(size_t *size);