drivers: Remove space between function name and '('
Change-Id: I42e995952a72a23a5f3aeadf428ad13f25546854 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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					committed by
					
						 Martin L Roth
						Martin L Roth
					
				
			
			
				
	
			
			
			
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							0d3a1fb93f
						
					
				
				
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					78d2469f05
				
			| @@ -16,7 +16,7 @@ | |||||||
| #error "FIXME: CALLOUT_ENTRY is UINT32 Data, not UINT Data" | #error "FIXME: CALLOUT_ENTRY is UINT32 Data, not UINT Data" | ||||||
| #endif | #endif | ||||||
|  |  | ||||||
| AGESA_STATUS GetBiosCallout (UINT32 Func, UINTN Data, VOID *ConfigPtr) | AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr) | ||||||
| { | { | ||||||
| 	AGESA_STATUS status; | 	AGESA_STATUS status; | ||||||
| 	UINTN i; | 	UINTN i; | ||||||
|   | |||||||
| @@ -171,14 +171,14 @@ enum | |||||||
| #define CIRRUS_HIDDEN_DAC_888COLOR 0xc5 | #define CIRRUS_HIDDEN_DAC_888COLOR 0xc5 | ||||||
|  |  | ||||||
| static void | static void | ||||||
| write_hidden_dac (uint8_t data) | write_hidden_dac(uint8_t data) | ||||||
| { | { | ||||||
| 	inb (0x3c8); | 	inb(0x3c8); | ||||||
| 	inb (0x3c6); | 	inb(0x3c6); | ||||||
| 	inb (0x3c6); | 	inb(0x3c6); | ||||||
| 	inb (0x3c6); | 	inb(0x3c6); | ||||||
| 	inb (0x3c6); | 	inb(0x3c6); | ||||||
| 	outb (data, 0x3c6); | 	outb(data, 0x3c6); | ||||||
| } | } | ||||||
|  |  | ||||||
| static void cirrus_init_linear_fb(struct device *dev) | static void cirrus_init_linear_fb(struct device *dev) | ||||||
| @@ -208,22 +208,22 @@ static void cirrus_init_linear_fb(struct device *dev) | |||||||
| 	printk(BIOS_DEBUG, "QEMU VGA: cirrus framebuffer @ %x (pci bar 0)\n", | 	printk(BIOS_DEBUG, "QEMU VGA: cirrus framebuffer @ %x (pci bar 0)\n", | ||||||
| 	       addr); | 	       addr); | ||||||
|  |  | ||||||
| 	vga_misc_write (VGA_IO_MISC_COLOR); | 	vga_misc_write(VGA_IO_MISC_COLOR); | ||||||
|  |  | ||||||
| 	vga_sr_write (VGA_SR_MEMORY_MODE, | 	vga_sr_write(VGA_SR_MEMORY_MODE, | ||||||
| 		      VGA_SR_MEMORY_MODE_NORMAL); | 		      VGA_SR_MEMORY_MODE_NORMAL); | ||||||
|  |  | ||||||
| 	vga_sr_write (VGA_SR_MAP_MASK_REGISTER, | 	vga_sr_write(VGA_SR_MAP_MASK_REGISTER, | ||||||
| 		      (1 << VGA_TEXT_TEXT_PLANE) | 		      (1 << VGA_TEXT_TEXT_PLANE) | ||||||
| 		      | (1 << VGA_TEXT_ATTR_PLANE)); | 		      | (1 << VGA_TEXT_ATTR_PLANE)); | ||||||
|  |  | ||||||
| 	vga_sr_write (VGA_SR_CLOCKING_MODE, | 	vga_sr_write(VGA_SR_CLOCKING_MODE, | ||||||
| 		      VGA_SR_CLOCKING_MODE_8_DOT_CLOCK); | 		      VGA_SR_CLOCKING_MODE_8_DOT_CLOCK); | ||||||
|  |  | ||||||
| 	vga_palette_disable(); | 	vga_palette_disable(); | ||||||
|  |  | ||||||
| 	/* Disable CR0-7 write protection.  */ | 	/* Disable CR0-7 write protection.  */ | ||||||
| 	vga_cr_write (VGA_CR_VSYNC_END, 0); | 	vga_cr_write(VGA_CR_VSYNC_END, 0); | ||||||
|  |  | ||||||
| 	overflow = ((vertical_total >> VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT) | 	overflow = ((vertical_total >> VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT) | ||||||
| 		    & VGA_CR_OVERFLOW_VERT_TOTAL1_MASK) | 		    & VGA_CR_OVERFLOW_VERT_TOTAL1_MASK) | ||||||
| @@ -248,56 +248,56 @@ static void cirrus_init_linear_fb(struct device *dev) | |||||||
| 		| ((line_compare >> VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT) | 		| ((line_compare >> VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT) | ||||||
| 		   & VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK); | 		   & VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK); | ||||||
|  |  | ||||||
| 	vga_cr_write (VGA_CR_HTOTAL, horizontal_total - 1); | 	vga_cr_write(VGA_CR_HTOTAL, horizontal_total - 1); | ||||||
| 	vga_cr_write (VGA_CR_HORIZ_END, horizontal_end - 1); | 	vga_cr_write(VGA_CR_HORIZ_END, horizontal_end - 1); | ||||||
| 	vga_cr_write (VGA_CR_HBLANK_START, horizontal_blank_start - 1); | 	vga_cr_write(VGA_CR_HBLANK_START, horizontal_blank_start - 1); | ||||||
| 	vga_cr_write (VGA_CR_HBLANK_END, horizontal_blank_end); | 	vga_cr_write(VGA_CR_HBLANK_END, horizontal_blank_end); | ||||||
| 	vga_cr_write (VGA_CR_HORIZ_SYNC_PULSE_START, | 	vga_cr_write(VGA_CR_HORIZ_SYNC_PULSE_START, | ||||||
| 		      horizontal_sync_pulse_start); | 		      horizontal_sync_pulse_start); | ||||||
| 	vga_cr_write (VGA_CR_HORIZ_SYNC_PULSE_END, | 	vga_cr_write(VGA_CR_HORIZ_SYNC_PULSE_END, | ||||||
| 		      horizontal_sync_pulse_end); | 		      horizontal_sync_pulse_end); | ||||||
| 	vga_cr_write (VGA_CR_VERT_TOTAL, vertical_total & 0xff); | 	vga_cr_write(VGA_CR_VERT_TOTAL, vertical_total & 0xff); | ||||||
| 	vga_cr_write (VGA_CR_OVERFLOW, overflow); | 	vga_cr_write(VGA_CR_OVERFLOW, overflow); | ||||||
| 	vga_cr_write (VGA_CR_CELL_HEIGHT, cell_height_reg); | 	vga_cr_write(VGA_CR_CELL_HEIGHT, cell_height_reg); | ||||||
| 	vga_cr_write (VGA_CR_VSYNC_START, vertical_sync_start & 0xff); | 	vga_cr_write(VGA_CR_VSYNC_START, vertical_sync_start & 0xff); | ||||||
| 	vga_cr_write (VGA_CR_VSYNC_END, vertical_sync_end & 0x0f); | 	vga_cr_write(VGA_CR_VSYNC_END, vertical_sync_end & 0x0f); | ||||||
| 	vga_cr_write (VGA_CR_VDISPLAY_END, vdisplay_end & 0xff); | 	vga_cr_write(VGA_CR_VDISPLAY_END, vdisplay_end & 0xff); | ||||||
| 	vga_cr_write (VGA_CR_PITCH, pitch & 0xff); | 	vga_cr_write(VGA_CR_PITCH, pitch & 0xff); | ||||||
| 	vga_cr_write (VGA_CR_VERTICAL_BLANK_START, vertical_blank_start & 0xff); | 	vga_cr_write(VGA_CR_VERTICAL_BLANK_START, vertical_blank_start & 0xff); | ||||||
| 	vga_cr_write (VGA_CR_VERTICAL_BLANK_END, vertical_blank_end & 0xff); | 	vga_cr_write(VGA_CR_VERTICAL_BLANK_END, vertical_blank_end & 0xff); | ||||||
| 	vga_cr_write (VGA_CR_LINE_COMPARE, line_compare & 0xff); | 	vga_cr_write(VGA_CR_LINE_COMPARE, line_compare & 0xff); | ||||||
|  |  | ||||||
| 	vga_gr_write (VGA_GR_MODE, VGA_GR_MODE_256_COLOR | VGA_GR_MODE_READ_MODE1); | 	vga_gr_write(VGA_GR_MODE, VGA_GR_MODE_256_COLOR | VGA_GR_MODE_READ_MODE1); | ||||||
| 	vga_gr_write (VGA_GR_GR6, VGA_GR_GR6_GRAPHICS_MODE); | 	vga_gr_write(VGA_GR_GR6, VGA_GR_GR6_GRAPHICS_MODE); | ||||||
|  |  | ||||||
| 	vga_sr_write (VGA_SR_MEMORY_MODE, VGA_SR_MEMORY_MODE_NORMAL); | 	vga_sr_write(VGA_SR_MEMORY_MODE, VGA_SR_MEMORY_MODE_NORMAL); | ||||||
|  |  | ||||||
| 	vga_cr_write (CIRRUS_CR_EXTENDED_DISPLAY, | 	vga_cr_write(CIRRUS_CR_EXTENDED_DISPLAY, | ||||||
| 		      (pitch >> CIRRUS_CR_EXTENDED_DISPLAY_PITCH_SHIFT) | 		      (pitch >> CIRRUS_CR_EXTENDED_DISPLAY_PITCH_SHIFT) | ||||||
| 		      & CIRRUS_CR_EXTENDED_DISPLAY_PITCH_MASK); | 		      & CIRRUS_CR_EXTENDED_DISPLAY_PITCH_MASK); | ||||||
|  |  | ||||||
| 	vga_cr_write (VGA_CR_MODE, VGA_CR_MODE_TIMING_ENABLE | 	vga_cr_write(VGA_CR_MODE, VGA_CR_MODE_TIMING_ENABLE | ||||||
| 		      | VGA_CR_MODE_BYTE_MODE | 		      | VGA_CR_MODE_BYTE_MODE | ||||||
| 		      | VGA_CR_MODE_NO_HERCULES | VGA_CR_MODE_NO_CGA); | 		      | VGA_CR_MODE_NO_HERCULES | VGA_CR_MODE_NO_CGA); | ||||||
|  |  | ||||||
| 	vga_cr_write (VGA_CR_START_ADDR_LOW_REGISTER, 0); | 	vga_cr_write(VGA_CR_START_ADDR_LOW_REGISTER, 0); | ||||||
| 	vga_cr_write (VGA_CR_START_ADDR_HIGH_REGISTER, 0); | 	vga_cr_write(VGA_CR_START_ADDR_HIGH_REGISTER, 0); | ||||||
|  |  | ||||||
| 	cr_ext = vga_cr_read (CIRRUS_CR_EXTENDED_DISPLAY); | 	cr_ext = vga_cr_read(CIRRUS_CR_EXTENDED_DISPLAY); | ||||||
| 	cr_ext &= ~(CIRRUS_CR_EXTENDED_DISPLAY_START_MASK1 | 	cr_ext &= ~(CIRRUS_CR_EXTENDED_DISPLAY_START_MASK1 | ||||||
| 		    | CIRRUS_CR_EXTENDED_DISPLAY_START_MASK2); | 		    | CIRRUS_CR_EXTENDED_DISPLAY_START_MASK2); | ||||||
| 	vga_cr_write (CIRRUS_CR_EXTENDED_DISPLAY, cr_ext); | 	vga_cr_write(CIRRUS_CR_EXTENDED_DISPLAY, cr_ext); | ||||||
|  |  | ||||||
| 	cr_overlay = vga_cr_read (CIRRUS_CR_EXTENDED_OVERLAY); | 	cr_overlay = vga_cr_read(CIRRUS_CR_EXTENDED_OVERLAY); | ||||||
| 	cr_overlay &= ~(CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_MASK); | 	cr_overlay &= ~(CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_MASK); | ||||||
| 	vga_cr_write (CIRRUS_CR_EXTENDED_OVERLAY, cr_overlay); | 	vga_cr_write(CIRRUS_CR_EXTENDED_OVERLAY, cr_overlay); | ||||||
|  |  | ||||||
| 	sr_ext = CIRRUS_SR_EXTENDED_MODE_LFB_ENABLE | 	sr_ext = CIRRUS_SR_EXTENDED_MODE_LFB_ENABLE | ||||||
| 		| CIRRUS_SR_EXTENDED_MODE_ENABLE_EXT | 		| CIRRUS_SR_EXTENDED_MODE_ENABLE_EXT | ||||||
| 		| CIRRUS_SR_EXTENDED_MODE_32BPP; | 		| CIRRUS_SR_EXTENDED_MODE_32BPP; | ||||||
| 	hidden_dac = CIRRUS_HIDDEN_DAC_888COLOR; | 	hidden_dac = CIRRUS_HIDDEN_DAC_888COLOR; | ||||||
| 	vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext); | 	vga_sr_write(CIRRUS_SR_EXTENDED_MODE, sr_ext); | ||||||
| 	write_hidden_dac (hidden_dac); | 	write_hidden_dac(hidden_dac); | ||||||
|  |  | ||||||
| 	fb_add_framebuffer_info(addr, width, height, 4 * width, 32); | 	fb_add_framebuffer_info(addr, width, height, 4 * width, 32); | ||||||
| } | } | ||||||
|   | |||||||
| @@ -93,6 +93,6 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) | |||||||
| 	for (i = 0; i < 128; i++) { | 	for (i = 0; i < 128; i++) { | ||||||
| 		printk(BIOS_SPEW, " %02x", edid[i]); | 		printk(BIOS_SPEW, " %02x", edid[i]); | ||||||
| 		if ((i & 0xf) == 0xf) | 		if ((i & 0xf) == 0xf) | ||||||
| 			printk (BIOS_SPEW, "\n"); | 			printk(BIOS_SPEW, "\n"); | ||||||
| 	} | 	} | ||||||
| } | } | ||||||
|   | |||||||
| @@ -44,7 +44,7 @@ drivers_lenovo_is_wacom_present(void) | |||||||
| 		return (result = 0); | 		return (result = 0); | ||||||
| 	} | 	} | ||||||
|  |  | ||||||
| 	superio = dev_find_slot_pnp (0x164e, 3); | 	superio = dev_find_slot_pnp(0x164e, 3); | ||||||
| 	if (!superio) { | 	if (!superio) { | ||||||
| 		printk(BIOS_INFO, "No Super I/O, skipping wacom\n"); | 		printk(BIOS_INFO, "No Super I/O, skipping wacom\n"); | ||||||
| 		return (result = 0); | 		return (result = 0); | ||||||
| @@ -60,9 +60,9 @@ drivers_lenovo_is_wacom_present(void) | |||||||
| 	pn = lenovo_mainboard_partnumber(); | 	pn = lenovo_mainboard_partnumber(); | ||||||
| 	if (!pn) | 	if (!pn) | ||||||
| 		return (result = 0); | 		return (result = 0); | ||||||
| 	printk (BIOS_DEBUG, "Lenovo P/N is %s\n", pn); | 	printk(BIOS_DEBUG, "Lenovo P/N is %s\n", pn); | ||||||
| 	for (i = 0; i < ARRAY_SIZE (tablet_numbers); i++) | 	for (i = 0; i < ARRAY_SIZE(tablet_numbers); i++) | ||||||
| 		if (memcmp (tablet_numbers[i], pn, 4) == 0) { | 		if (memcmp(tablet_numbers[i], pn, 4) == 0) { | ||||||
| 			printk(BIOS_DEBUG, "Lenovo P/N %s is a tablet\n", pn); | 			printk(BIOS_DEBUG, "Lenovo P/N %s is a tablet\n", pn); | ||||||
| 			return (result = 1); | 			return (result = 1); | ||||||
| 		} | 		} | ||||||
|   | |||||||
| @@ -19,7 +19,7 @@ static void *nc_fpga_bar0; | |||||||
| 		dst = ((typeof(dst))var); \ | 		dst = ((typeof(dst))var); \ | ||||||
| } | } | ||||||
|  |  | ||||||
| static void init_temp_mon (void *base_adr) | static void init_temp_mon(void *base_adr) | ||||||
| { | { | ||||||
| 	uint32_t cc[5], i = 0; | 	uint32_t cc[5], i = 0; | ||||||
| 	uint8_t num = 0; | 	uint8_t num = 0; | ||||||
| @@ -48,7 +48,7 @@ static void init_temp_mon (void *base_adr) | |||||||
| 	FPGA_SET_PARAM(T_Crit, ctrl->t_crit); | 	FPGA_SET_PARAM(T_Crit, ctrl->t_crit); | ||||||
| } | } | ||||||
|  |  | ||||||
| static void init_fan_ctrl (void *base_adr) | static void init_fan_ctrl(void *base_adr) | ||||||
| { | { | ||||||
| 	uint8_t mask = 0, freeze_disable = 0, fan_req = 0; | 	uint8_t mask = 0, freeze_disable = 0, fan_req = 0; | ||||||
| 	volatile fan_ctrl_t *ctrl = (fan_ctrl_t *)base_adr; | 	volatile fan_ctrl_t *ctrl = (fan_ctrl_t *)base_adr; | ||||||
|   | |||||||
| @@ -91,7 +91,7 @@ unsigned int spi_crop_chunk(const struct spi_slave *slave, unsigned int cmd_len, | |||||||
| 	deduct_opcode_len = !!(ctrlr->flags & SPI_CNTRLR_DEDUCT_OPCODE_LEN); | 	deduct_opcode_len = !!(ctrlr->flags & SPI_CNTRLR_DEDUCT_OPCODE_LEN); | ||||||
| 	ctrlr_max = ctrlr->max_xfer_size; | 	ctrlr_max = ctrlr->max_xfer_size; | ||||||
|  |  | ||||||
| 	assert (ctrlr_max != 0); | 	assert(ctrlr_max != 0); | ||||||
|  |  | ||||||
| 	/* Assume opcode is always one byte and deduct it from the cmd_len | 	/* Assume opcode is always one byte and deduct it from the cmd_len | ||||||
| 	   as the hardware has a separate register for the opcode. */ | 	   as the hardware has a separate register for the opcode. */ | ||||||
|   | |||||||
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