Updated ep405pc to latest config system.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/ppc/ppc4xx/Config.lb

@@ -20,8 +20,10 @@ initobject cache.S
 initobject sdram.c
 initobject clock.c
 
-object mem.o
+config chip.h
 object clock.o
 object cache.S
+object pci_domain.o
+driver pci_bridge.o
 
 dir /cpu/simple_init

src/cpu/ppc/ppc4xx/chip.h

@@ -0,0 +1,4 @@
+struct cpu_ppc_ppc4xx_config
+{
+};
+extern struct chip_operations cpu_ppc_ppc4xx_ops;

src/cpu/ppc/ppc4xx/pci_bridge.c

@@ -0,0 +1,34 @@
+/*
+ * Initialisation of the PCI bridge .
+ */
+
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+
+static void 
+pci_bridge_enable(struct device *dev)
+{
+	printk_info("Configure PCI Bridge\n");
+
+	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER);
+	pci_write_config16(dev, 0x60, 0x0f00);
+
+	printk_info("PCI Bridge configuration complete\n");
+}
+
+struct device_operations pci_bridge_ops  = {
+        .read_resources   = pci_dev_read_resources,
+        .set_resources    = pci_dev_set_resources,
+        .enable_resources = pci_dev_enable_resources,
+        .enable           = pci_bridge_enable,
+        .scan_bus         = 0,
+};
+
+struct pci_driver pci_bridge_pci_driver __pci_driver = {
+	/* w83c553f */
+	.ops = &pci_bridge_ops,
+	.device = PCI_DEVICE_ID_IBM_405GP,
+	.vendor = PCI_VENDOR_ID_IBM,
+};

src/cpu/ppc/ppc4xx/pci_domain.c

@@ -0,0 +1,74 @@
+/*
+ * Initialisation of the PCI bridge .
+ */
+
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+	max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+	return max;
+}
+
+static void pci_domain_read_resources(device_t dev)
+{
+	struct resource *resource;
+
+	/* Initialize the system wide io space constraints */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
+	resource->limit = 0xffffUL;
+	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+	/* Initialize the system wide memory resources constraints */
+	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
+	resource->limit = 0xffffffffULL;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+        unsigned long basek, unsigned long sizek)
+{
+	struct resource *resource;
+
+	if (!sizek) {
+		return;
+	}
+	resource = new_resource(dev, index);
+	resource->base  = ((resource_t)basek) << 10;
+	resource->size  = ((resource_t)sizek) << 10;
+	resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+	int idx = 3; /* who knows? */
+
+	ram_resource(dev, idx, 0, EMBEDDED_RAM_SIZE>>10);
+	assign_resources(&dev->link[0]);
+}
+
+struct device_operations pci_domain_ops  = {
+        .read_resources   = pci_domain_read_resources,
+        .set_resources    = pci_domain_set_resources,
+        .enable_resources = enable_childrens_resources,
+        .init             = 0,
+        .scan_bus         = pci_domain_scan_bus,
+	.ops_pci_bus	  = &pci_ppc_conf1
+};
+
+static void enable_dev(struct device *dev)
+{
+        /* Set the operations if it is a special bus type */
+        if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+                dev->ops = &pci_domain_ops;
+        }
+}
+
+struct chip_operations cpu_ppc_ppc4xx_ops = {
+        CHIP_NAME("PPC 4XX CPU")
+        .enable_dev = enable_dev,
+};