diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index 4e23c5bb30..f9aff3955a 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -62,7 +62,11 @@
 #define CPUID_ALDERLAKE_N_A0		0xb06e0
 #define CPUID_METEORLAKE_A0_1		0xa06a0
 #define CPUID_METEORLAKE_A0_2		0xa06a1
-#define CPUID_RAPTORLAKE_P_J0		0xb06a2
-#define CPUID_RAPTORLAKE_P_Q0		0xb06a3
+#define CPUID_RAPTORLAKE_E_S_HX_B0	0xb0671
+#define CPUID_RAPTORLAKE_HX_S_8_8_C0	0xb06f2
+#define CPUID_RAPTORLAKE_H_P_J0		0xb06a2
+#define CPUID_RAPTORLAKE_S_6_0_C0	0xb06f5
+#define CPUID_RAPTORLAKE_S_A0		0xb0670
+#define CPUID_RAPTORLAKE_U_Q0		0xb06a3
 
 #endif /* CPU_INTEL_CPU_IDS_H */
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 15a41ce072..4895ce4ed9 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3983,6 +3983,10 @@
 #define PCI_DID_INTEL_MTL_P_GT2_2			0x7d50
 #define PCI_DID_INTEL_MTL_P_GT2_3			0x7d55
 #define PCI_DID_INTEL_MTL_P_GT2_4			0x7d60
+#define PCI_DID_INTEL_RPL_HX_GT1			0xa788
+#define PCI_DID_INTEL_RPL_HX_GT2			0xa78b
+#define PCI_DID_INTEL_RPL_HX_GT3			0x4688
+#define PCI_DID_INTEL_RPL_HX_GT4			0x468b
 #define PCI_DID_INTEL_RPL_P_GT1				0xa720
 #define PCI_DID_INTEL_RPL_P_GT2				0xa7a8
 #define PCI_DID_INTEL_RPL_P_GT3				0xa7a0
@@ -4106,6 +4110,14 @@
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
 #define PCI_DID_INTEL_MTL_P_ID_3		0x7d14
 #define PCI_DID_INTEL_MTL_P_ID_4		0x7d15
+#define PCI_DID_INTEL_RPL_HX_ID_1		0xa702
+#define PCI_DID_INTEL_RPL_HX_ID_2		0xa729
+#define PCI_DID_INTEL_RPL_HX_ID_3		0xa728
+#define PCI_DID_INTEL_RPL_HX_ID_4		0xa72a
+#define PCI_DID_INTEL_RPL_HX_ID_5		0xa719
+#define PCI_DID_INTEL_RPL_HX_ID_6		0x4637
+#define PCI_DID_INTEL_RPL_HX_ID_7		0x463b
+#define PCI_DID_INTEL_RPL_HX_ID_8		0x4647
 #define PCI_DID_INTEL_RPL_P_ID_1		0xa706
 #define PCI_DID_INTEL_RPL_P_ID_2		0xa707
 #define PCI_DID_INTEL_RPL_P_ID_3		0xa708
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c
index cc82838799..9887eaa5b8 100644
--- a/src/soc/intel/alderlake/bootblock/report_platform.c
+++ b/src/soc/intel/alderlake/bootblock/report_platform.c
@@ -34,8 +34,10 @@ static struct {
 	{ CPUID_ALDERLAKE_S_C0, "Alderlake-S C0 Platform" },
 	{ CPUID_ALDERLAKE_S_G0, "Alderlake-S G0 Platform" },
 	{ CPUID_ALDERLAKE_S_H0, "Alderlake-S H0 Platform" },
-	{ CPUID_RAPTORLAKE_P_J0, "Raptorlake-P J0 Platform" },
-	{ CPUID_RAPTORLAKE_P_Q0, "Raptorlake-P Q0 Platform" },
+	{ CPUID_RAPTORLAKE_E_S_HX_B0, "Raptorlake B0 Platform" },
+	{ CPUID_RAPTORLAKE_HX_S_8_8_C0, "Raptorlake C0 Platform" },
+	{ CPUID_RAPTORLAKE_H_P_J0, "Raptorlake J0 Platform" },
+	{ CPUID_RAPTORLAKE_U_Q0, "Raptorlake-U Q0 Platform" },
 };
 
 static struct {
@@ -71,6 +73,14 @@ static struct {
 	{ PCI_DID_INTEL_ADL_S_ID_12, "Alderlake-S (2+0)" },
 	{ PCI_DID_INTEL_ADL_S_ID_13, "Alderlake-S" },
 	{ PCI_DID_INTEL_ADL_S_ID_14, "Alderlake-S" },
+	{ PCI_DID_INTEL_RPL_HX_ID_1, "Raptorlake-HX (8+16)" },
+	{ PCI_DID_INTEL_RPL_HX_ID_2, "Raptorlake-HX (8+12)" },
+	{ PCI_DID_INTEL_RPL_HX_ID_3, "Raptorlake-HX (8+8)" },
+	{ PCI_DID_INTEL_RPL_HX_ID_4, "Raptorlake-HX (6+8)" },
+	{ PCI_DID_INTEL_RPL_HX_ID_5, "Raptorlake-HX (6+4)" },
+	{ PCI_DID_INTEL_RPL_HX_ID_6, "Raptorlake-HX (8+8)" },
+	{ PCI_DID_INTEL_RPL_HX_ID_7, "Raptorlake-HX (6+8)" },
+	{ PCI_DID_INTEL_RPL_HX_ID_8, "Raptorlake-HX (4+4)" },
 	{ PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" },
 	{ PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" },
 	{ PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" },
@@ -199,6 +209,10 @@ static struct {
 	{ PCI_DID_INTEL_ADL_S_GT2,   "Alderlake S GT2" },
 	{ PCI_DID_INTEL_ADL_S_GT2_1, "Alderlake S GT2" },
 	{ PCI_DID_INTEL_ADL_S_GT2_2, "Alderlake S GT2" },
+	{ PCI_DID_INTEL_RPL_HX_GT1, "Raptorlake HX GT1" },
+	{ PCI_DID_INTEL_RPL_HX_GT2, "Raptorlake HX GT2" },
+	{ PCI_DID_INTEL_RPL_HX_GT3, "Raptorlake HX GT3" },
+	{ PCI_DID_INTEL_RPL_HX_GT4, "Raptorlake HX GT4" },
 	{ PCI_DID_INTEL_RPL_P_GT1, "Raptorlake P GT1" },
 	{ PCI_DID_INTEL_RPL_P_GT2, "Raptorlake P GT2" },
 	{ PCI_DID_INTEL_RPL_P_GT3, "Raptorlake P GT3" },
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 27c6a9330d..d78fc7ad5b 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -239,6 +239,16 @@ enum adl_cpu_type get_adl_cpu_type(void)
 		PCI_DID_INTEL_ADL_N_ID_4,
 	};
 
+	const uint16_t rpl_hx_mch_ids[] = {
+		PCI_DID_INTEL_RPL_HX_ID_1,
+		PCI_DID_INTEL_RPL_HX_ID_2,
+		PCI_DID_INTEL_RPL_HX_ID_3,
+		PCI_DID_INTEL_RPL_HX_ID_4,
+		PCI_DID_INTEL_RPL_HX_ID_5,
+		PCI_DID_INTEL_RPL_HX_ID_6,
+		PCI_DID_INTEL_RPL_HX_ID_7,
+		PCI_DID_INTEL_RPL_HX_ID_8,
+	};
 	const uint16_t rpl_p_mch_ids[] = {
 		PCI_DID_INTEL_RPL_P_ID_1,
 		PCI_DID_INTEL_RPL_P_ID_2,
@@ -271,6 +281,11 @@ enum adl_cpu_type get_adl_cpu_type(void)
 			return ADL_N;
 	}
 
+	for (size_t i = 0; i < ARRAY_SIZE(rpl_hx_mch_ids); i++) {
+		if (rpl_hx_mch_ids[i] == mchid)
+			return RPL_HX;
+	}
+
 	for (size_t i = 0; i < ARRAY_SIZE(rpl_p_mch_ids); i++) {
 		if (rpl_p_mch_ids[i] == mchid)
 			return RPL_P;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index ee8ef89a0f..7859ca6e3b 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -535,6 +535,14 @@ static uint16_t get_vccin_aux_imon_iccmax(void)
 	case PCI_DID_INTEL_ADL_S_ID_10:
 	case PCI_DID_INTEL_ADL_S_ID_11:
 	case PCI_DID_INTEL_ADL_S_ID_12:
+	case PCI_DID_INTEL_RPL_HX_ID_1:
+	case PCI_DID_INTEL_RPL_HX_ID_2:
+	case PCI_DID_INTEL_RPL_HX_ID_3:
+	case PCI_DID_INTEL_RPL_HX_ID_4:
+	case PCI_DID_INTEL_RPL_HX_ID_5:
+	case PCI_DID_INTEL_RPL_HX_ID_6:
+	case PCI_DID_INTEL_RPL_HX_ID_7:
+	case PCI_DID_INTEL_RPL_HX_ID_8:
 		return ICC_MAX_ADL_S;
 	default:
 		printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n",
diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h
index 424e02a6aa..19a8db10e6 100644
--- a/src/soc/intel/alderlake/include/soc/cpu.h
+++ b/src/soc/intel/alderlake/include/soc/cpu.h
@@ -25,7 +25,11 @@ enum adl_cpu_type {
 	ADL_N,
 	ADL_P,
 	ADL_S,
+	RPL_H,
+	RPL_HX,
 	RPL_P,
+	RPL_S,
+	RPL_U,
 };
 
 enum adl_cpu_type get_adl_cpu_type(void);
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 4636b3b609..a8c04dbaa9 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -79,8 +79,12 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 },
 	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 },
 	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 },
-	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_J0 },
-	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_Q0 },
+	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_E_S_HX_B0 },
+	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_HX_S_8_8_C0 },
+	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_H_P_J0 },
+	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_6_0_C0 },
+	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_A0 },
+	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_U_Q0 },
 	{ 0, 0 },
 };
 
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index aeeff123c9..c54154e275 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -435,6 +435,14 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_ADL_N_ID_2,
 	PCI_DID_INTEL_ADL_N_ID_3,
 	PCI_DID_INTEL_ADL_N_ID_4,
+	PCI_DID_INTEL_RPL_HX_ID_1,
+	PCI_DID_INTEL_RPL_HX_ID_2,
+	PCI_DID_INTEL_RPL_HX_ID_3,
+	PCI_DID_INTEL_RPL_HX_ID_4,
+	PCI_DID_INTEL_RPL_HX_ID_5,
+	PCI_DID_INTEL_RPL_HX_ID_6,
+	PCI_DID_INTEL_RPL_HX_ID_7,
+	PCI_DID_INTEL_RPL_HX_ID_8,
 	PCI_DID_INTEL_RPL_P_ID_1,
 	PCI_DID_INTEL_RPL_P_ID_2,
 	PCI_DID_INTEL_RPL_P_ID_3,