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lynxpoint: Fix GPIO and PM base reservations

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The kernel ACPI was not happy with the Add inside a
ResourceTemplate (or perhaps within the IO declaration)

Instead make a buffer of IO reservations and turn _CRS
into a method that updates the buffer depending on the
chipset type.

This adds an \ISLP() method that checks the chipset LPC
device ID to see if it is -LP or -H.

It also increases the PM base reservation to 256 bytes
and moves both GPIO and PM base to above 0x1000 on -LP
chipsets.

Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2815
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Duncan Laurie
2013-03-08 16:34:33 -08:00
committed by Ronald G. Minnich
parent f5966b14e8
commit 7922b468b5
4 changed files with 90 additions and 33 deletions
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4
src/southbridge/intel/lynxpoint/lpc.c
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@@ -630,11 +630,11 @@ static void pch_lpc_add_io_resources(device_t dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* GPIOBASE */
pch_lpc_add_io_resource(dev, DEFAULT_GPIOBASE, DEFAULT_GPIOSIZE,
pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE,
GPIO_BASE);
/* PMBASE */
pch_lpc_add_io_resource(dev, DEFAULT_PMBASE, 128, PMBASE);
pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE);
/* LPC Generic IO Decode range. */
pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);