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soc/intel/apollolake: Clean up code by using common System Agent module

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This patch currently contains the SA initialization
required for bootblock phase -

1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code.
2. Perform PCIEXBAR programming based on soc configurable
    PCIEX_LENGTH_xxxMB
3. Use common systemagent header file.

Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Subrata Banik
2017-03-14 18:26:27 +05:30
committed by Martin Roth
parent 93ebe499d4
commit 7952e283fb
7 changed files with 16 additions and 32 deletions
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8
src/soc/intel/apollolake/Kconfig
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@@ -41,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS
select PCIEXP_COMMON_CLOCK
select PCIEXP_CLK_PM
select PCIEXP_L1_SUB_STATE
select PCIEX_LENGTH_256MB
select POSTCAR_CONSOLE
select POSTCAR_STAGE
select REG_SCRIPT
@@ -51,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_SMI
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
@@ -89,10 +91,6 @@ config SOC_INTEL_COMMON_RESET
bool
default y
config MMCONF_BASE_ADDRESS
hex "PCI MMIO Base Address"
default 0xe0000000
config IOSF_BASE_ADDRESS
hex "MMIO Base Address of sideband bus"
default 0xd0000000
@@ -283,7 +281,7 @@ config USE_APOLLOLAKE_FSP_CAR
bool "Use FSP CAR"
select FSP_CAR
help
Use FSP APIs to initialize & tear Down the Cache-As-Ram.
Use FSP APIs to initialize & tear down the Cache-As-Ram.
endchoice