src: capitalize 'PCIe'

Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/baytrail/acpi/globalnvs.asl

@@ -99,7 +99,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PAVP,	 8,	// 0xe9 - IGD PAVP data
 	Offset (0xeb),
 	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native pcie support
+	NPCE,	 8,	// 0xec - native PCIe support
 	PLFL,	 8,	// 0xed - platform flavor
 	BREV,	 8,	// 0xee - board revision
 	DPBM,	 8,	// 0xef - digital port b mode

src/soc/intel/baytrail/include/soc/nvs.h

@@ -83,7 +83,7 @@ typedef struct global_nvs_t {
 	u8	pavp; /* 0xe9 - IGD PAVP data */
 	u8	rsvd12; /* 0xea - rsvd */
 	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native pcie support */
+	u8	npce; /* 0xec - native PCIe support */
 	u8	plfl; /* 0xed - platform flavor */
 	u8	brev; /* 0xee - board revision */
 	u8	dpbm; /* 0xef - digital port b mode */

src/soc/intel/baytrail/pcie.c

@@ -163,7 +163,7 @@ static u8 all_ports_no_dev_present(struct device *dev)
 		dev->path.pci.devfn &= ~0x7;
 		dev->path.pci.devfn |= func;
 
-		/* is pcie device there */
+		/* is PCIe device there */
 		if (pci_read_config32(dev, 0) == 0xFFFFFFFF)
 			continue;