src: capitalize 'PCIe'

Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/skylake/acpi/globalnvs.asl

@@ -106,7 +106,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PAVP,	 8,	// 0xe9 - IGD PAVP data
 	Offset (0xeb),
 	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native pcie support
+	NPCE,	 8,	// 0xec - native PCIe support
 	PLFL,	 8,	// 0xed - platform flavor
 	BREV,	 8,	// 0xee - board revision
 	DPBM,	 8,	// 0xef - digital port b mode

src/soc/intel/skylake/chip.h

@@ -226,7 +226,7 @@ struct soc_intel_skylake_config {
 	u8 PchDciEn;
 
 	/*
-	 * Pcie Root Port configuration:
+	 * PCIe Root Port configuration:
 	 * each element of array corresponds to
 	 * respective PCIe root port.
 	 */

src/soc/intel/skylake/include/soc/nvs.h

@@ -88,7 +88,7 @@ typedef struct global_nvs_t {
 	u8	pavp; /* 0xe9 - IGD PAVP data */
 	u8	rsvd12; /* 0xea - rsvd */
 	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native pcie support */
+	u8	npce; /* 0xec - native PCIe support */
 	u8	plfl; /* 0xed - platform flavor */
 	u8	brev; /* 0xee - board revision */
 	u8	dpbm; /* 0xef - digital port b mode */