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src: capitalize 'PCIe'

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Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS
2020-02-24 13:43:39 +01:00
committed by Patrick Georgi
parent f3161df2eb
commit 79ccc69332
28 changed files with 30 additions and 30 deletions
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2
src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
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@@ -166,7 +166,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
NPCE, 8, // 0xec - native pcie support
NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode

2
src/southbridge/intel/bd82x6x/nvs.h
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@@ -138,7 +138,7 @@ typedef struct global_nvs_t {
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
u8 npce; /* 0xec - native pcie support */
u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */

4
src/southbridge/intel/bd82x6x/pch.c
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@@ -351,8 +351,8 @@ static void pch_pcie_enable(struct device *dev)
* If PCIe 0-3 disabled set Function 0 0xE2[0] = 1
* If PCIe 4-7 disabled set Function 4 0xE2[0] = 1
*
* This check is done here instead of pcie driver
* because the pcie driver enable() handler is not
* This check is done here instead of PCIe driver
* because the PCIe driver enable() handler is not
* called unless the device is enabled.
*/
if ((PCI_FUNC(dev->path.pci.devfn) == 0 ||

2
src/southbridge/intel/ibexpeak/nvs.h
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@@ -137,7 +137,7 @@ typedef struct global_nvs_t {
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
u8 npce; /* 0xec - native pcie support */
u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */

2
src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
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@@ -161,7 +161,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PAVP, 8, // 0xe9 - IGD PAVP data
Offset (0xeb),
OSCC, 8, // 0xeb - PCIe OSC control
NPCE, 8, // 0xec - native pcie support
NPCE, 8, // 0xec - native PCIe support
PLFL, 8, // 0xed - platform flavor
BREV, 8, // 0xee - board revision
DPBM, 8, // 0xef - digital port b mode

2
src/southbridge/intel/lynxpoint/nvs.h
View File

@@ -114,7 +114,7 @@ typedef struct global_nvs_t {
u8 pavp; /* 0xe9 - IGD PAVP data */
u8 rsvd12; /* 0xea - rsvd */
u8 oscc; /* 0xeb - PCIe OSC control */
u8 npce; /* 0xec - native pcie support */
u8 npce; /* 0xec - native PCIe support */
u8 plfl; /* 0xed - platform flavor */
u8 brev; /* 0xee - board revision */
u8 dpbm; /* 0xef - digital port b mode */