src: capitalize 'PCIe'

Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/cpu/amd/agesa/family14/fixme.c

@@ -100,7 +100,7 @@ void amd_initenv(void)
 	PciValue |= 0x80000000;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
-	/* Initialize GMM Base Address for Pcie Mode
+	/* Initialize GMM Base Address for PCIe Mode
 	 *      Modify B0D1F0x18
 	 */
 	PciAddress.Address.Bus = 0;
@@ -112,7 +112,7 @@ void amd_initenv(void)
 	PciValue |= 0x96000000;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
-	/* Initialize FB Base Address for Pcie Mode
+	/* Initialize FB Base Address for PCIe Mode
 	 *      Modify B0D1F0x10
 	 */
 	PciAddress.Address.Register = 0x10;

src/mainboard/asrock/e350m1/acpi/routing.asl

@@ -199,7 +199,7 @@ Scope(\_SB) {
 		/* Package(){0x00140005, 1, 0, 17 }, */
 		/* Package(){0x00140006, 1, 0, 17 }, */
 
-		/* TODO: pcie */
+		/* TODO: PCIe */
 		Package(){0x0015FFFF, 0, 0, 16 },
 		Package(){0x0015FFFF, 1, 0, 17 },
 		Package(){0x0015FFFF, 2, 0, 18 },

src/mainboard/asus/f2a85-m/acpi/routing.asl

@@ -78,7 +78,7 @@
 		/* Bus 0, Dev 17 - SATA controller */
 		Package(){0x0011FFFF, 0, INTD, 0 },
 
-		/* Bus 0, Dev 21 Pcie Bridge */
+		/* Bus 0, Dev 21 PCIe Bridge */
 		Package(){0x0015FFFF, 0, INTA, 0 },
 		Package(){0x0015FFFF, 1, INTB, 0 },
 		Package(){0x0015FFFF, 2, INTC, 0 },

src/mainboard/gizmosphere/gizmo/acpi/routing.asl

@@ -200,7 +200,7 @@ Scope(\_SB) {
 		/* Package(){0x00140005, 1, 0, 17 }, */
 		/* Package(){0x00140006, 1, 0, 17 }, */
 
-		/* TODO: pcie */
+		/* TODO: PCIe */
 		Package(){0x0015FFFF, 0, 0, 16 },
 		Package(){0x0015FFFF, 1, 0, 17 },
 		Package(){0x0015FFFF, 2, 0, 18 },

src/mainboard/hp/pavilion_m6_1035dx/acpi/routing.asl

@@ -90,7 +90,7 @@
 		/* Bus 0, Dev 17 - SATA controller */
 		Package(){0x0011FFFF, 0, INTD, 0 },
 
-		/* Bus 0, Dev 21 Pcie Bridge */
+		/* Bus 0, Dev 21 PCIe Bridge */
 		Package(){0x0015FFFF, 0, INTA, 0 },
 		Package(){0x0015FFFF, 1, INTB, 0 },
 		Package(){0x0015FFFF, 2, INTC, 0 },

src/mainboard/lenovo/g505s/acpi/routing.asl

@@ -90,7 +90,7 @@
 		/* Bus 0, Dev 17 - SATA controller */
 		Package(){0x0011FFFF, 0, INTD, 0 },
 
-		/* Bus 0, Dev 21 Pcie Bridge */
+		/* Bus 0, Dev 21 PCIe Bridge */
 		Package(){0x0015FFFF, 0, INTA, 0 },
 		Package(){0x0015FFFF, 1, INTB, 0 },
 		Package(){0x0015FFFF, 2, INTC, 0 },

src/mainboard/msi/ms7721/acpi/routing.asl

@@ -71,7 +71,7 @@
 		/* Bus 0, Dev 17 - SATA controller */
 		Package(){0x0011FFFF, 0, INTD, 0 },
 
-		/* Bus 0, Dev 21 Pcie Bridge */
+		/* Bus 0, Dev 21 PCIe Bridge */
 		Package(){0x0015FFFF, 0, INTA, 0 },
 		Package(){0x0015FFFF, 1, INTB, 0 },
 		Package(){0x0015FFFF, 2, INTC, 0 },

src/mainboard/pcengines/apu1/acpi/routing.asl

@@ -162,7 +162,7 @@ Scope(\_SB) {
 		/* Package(){0x00140005, 1, 0, 17 }, */
 		/* Package(){0x00140006, 1, 0, 17 }, */
 
-		/* TODO: pcie */
+		/* TODO: PCIe */
 		Package(){0x0015FFFF, 0, 0, 16 },
 		Package(){0x0015FFFF, 1, 0, 17 },
 		Package(){0x0015FFFF, 2, 0, 18 },

src/soc/intel/baytrail/acpi/globalnvs.asl

@@ -99,7 +99,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PAVP,	 8,	// 0xe9 - IGD PAVP data
 	Offset (0xeb),
 	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native pcie support
+	NPCE,	 8,	// 0xec - native PCIe support
 	PLFL,	 8,	// 0xed - platform flavor
 	BREV,	 8,	// 0xee - board revision
 	DPBM,	 8,	// 0xef - digital port b mode

src/soc/intel/baytrail/include/soc/nvs.h

@@ -83,7 +83,7 @@ typedef struct global_nvs_t {
 	u8	pavp; /* 0xe9 - IGD PAVP data */
 	u8	rsvd12; /* 0xea - rsvd */
 	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native pcie support */
+	u8	npce; /* 0xec - native PCIe support */
 	u8	plfl; /* 0xed - platform flavor */
 	u8	brev; /* 0xee - board revision */
 	u8	dpbm; /* 0xef - digital port b mode */

src/soc/intel/baytrail/pcie.c

@@ -163,7 +163,7 @@ static u8 all_ports_no_dev_present(struct device *dev)
 		dev->path.pci.devfn &= ~0x7;
 		dev->path.pci.devfn |= func;
 
-		/* is pcie device there */
+		/* is PCIe device there */
 		if (pci_read_config32(dev, 0) == 0xFFFFFFFF)
 			continue;
 

src/soc/intel/braswell/acpi/globalnvs.asl

@@ -101,7 +101,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PAVP,	 8,	// 0xe9 - IGD PAVP data
 	Offset (0xeb),
 	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native pcie support
+	NPCE,	 8,	// 0xec - native PCIe support
 	PLFL,	 8,	// 0xed - platform flavor
 	BREV,	 8,	// 0xee - board revision
 	DPBM,	 8,	// 0xef - digital port b mode

src/soc/intel/braswell/include/soc/nvs.h

@@ -86,7 +86,7 @@ typedef struct global_nvs_t {
 	u8	pavp; /* 0xe9 - IGD PAVP data */
 	u8	rsvd12; /* 0xea - rsvd */
 	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native pcie support */
+	u8	npce; /* 0xec - native PCIe support */
 	u8	plfl; /* 0xed - platform flavor */
 	u8	brev; /* 0xee - board revision */
 	u8	dpbm; /* 0xef - digital port b mode */

src/soc/intel/broadwell/acpi/globalnvs.asl

@@ -91,7 +91,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PAVP,	 8,	// 0xe9 - IGD PAVP data
 	Offset (0xeb),
 	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native pcie support
+	NPCE,	 8,	// 0xec - native PCIe support
 	PLFL,	 8,	// 0xed - platform flavor
 	BREV,	 8,	// 0xee - board revision
 	DPBM,	 8,	// 0xef - digital port b mode

src/soc/intel/broadwell/include/soc/nvs.h

@@ -75,7 +75,7 @@ typedef struct global_nvs_t {
 	u8	pavp; /* 0xe9 - IGD PAVP data */
 	u8	rsvd2; /* 0xea - rsvd */
 	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native pcie support */
+	u8	npce; /* 0xec - native PCIe support */
 	u8	plfl; /* 0xed - platform flavor */
 	u8	brev; /* 0xee - board revision */
 	u8	dpbm; /* 0xef - digital port b mode */

src/soc/intel/cannonlake/chip.h

@@ -180,7 +180,7 @@ struct soc_intel_cannonlake_config {
 
 	/* PCIe Root Ports */
 	uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
-	/* PCIe output clocks type to Pcie devices.
+	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */
 	uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];

src/soc/intel/denverton_ns/smm.c

@@ -53,7 +53,7 @@ void smm_southbridge_enable_smi(void)
 {
 
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
-	/* Configure events Disable pcie wake. */
+	/* Configure events Disable PCIe wake. */
 	enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
 	disable_gpe(PME_B0_EN);
 

src/soc/intel/icelake/chip.h

@@ -134,7 +134,7 @@ struct soc_intel_icelake_config {
 
 	/* PCIe Root Ports */
 	uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
-	/* PCIe output clocks type to Pcie devices.
+	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */
 	uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];

src/soc/intel/skylake/acpi/globalnvs.asl

@@ -106,7 +106,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PAVP,	 8,	// 0xe9 - IGD PAVP data
 	Offset (0xeb),
 	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native pcie support
+	NPCE,	 8,	// 0xec - native PCIe support
 	PLFL,	 8,	// 0xed - platform flavor
 	BREV,	 8,	// 0xee - board revision
 	DPBM,	 8,	// 0xef - digital port b mode

src/soc/intel/skylake/chip.h

@@ -226,7 +226,7 @@ struct soc_intel_skylake_config {
 	u8 PchDciEn;
 
 	/*
-	 * Pcie Root Port configuration:
+	 * PCIe Root Port configuration:
 	 * each element of array corresponds to
 	 * respective PCIe root port.
 	 */

src/soc/intel/skylake/include/soc/nvs.h

@@ -88,7 +88,7 @@ typedef struct global_nvs_t {
 	u8	pavp; /* 0xe9 - IGD PAVP data */
 	u8	rsvd12; /* 0xea - rsvd */
 	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native pcie support */
+	u8	npce; /* 0xec - native PCIe support */
 	u8	plfl; /* 0xed - platform flavor */
 	u8	brev; /* 0xee - board revision */
 	u8	dpbm; /* 0xef - digital port b mode */

src/soc/intel/tigerlake/chip.h

@@ -114,7 +114,7 @@ struct soc_intel_tigerlake_config {
 
 	/* PCIe Root Ports */
 	uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
-	/* PCIe output clocks type to Pcie devices.
+	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */
 	uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];

src/southbridge/intel/bd82x6x/acpi/globalnvs.asl

@@ -166,7 +166,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PAVP,	 8,	// 0xe9 - IGD PAVP data
 	Offset (0xeb),
 	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native pcie support
+	NPCE,	 8,	// 0xec - native PCIe support
 	PLFL,	 8,	// 0xed - platform flavor
 	BREV,	 8,	// 0xee - board revision
 	DPBM,	 8,	// 0xef - digital port b mode

src/southbridge/intel/bd82x6x/nvs.h

@@ -138,7 +138,7 @@ typedef struct global_nvs_t {
 	u8	pavp; /* 0xe9 - IGD PAVP data */
 	u8	rsvd12; /* 0xea - rsvd */
 	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native pcie support */
+	u8	npce; /* 0xec - native PCIe support */
 	u8	plfl; /* 0xed - platform flavor */
 	u8	brev; /* 0xee - board revision */
 	u8	dpbm; /* 0xef - digital port b mode */

src/southbridge/intel/bd82x6x/pch.c

@@ -351,8 +351,8 @@ static void pch_pcie_enable(struct device *dev)
 		 * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1
 		 * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1
 		 *
-		 * This check is done here instead of pcie driver
+		 * This check is done here instead of PCIe driver
-		 * because the pcie driver enable() handler is not
+		 * because the PCIe driver enable() handler is not
 		 * called unless the device is enabled.
 		 */
 		if ((PCI_FUNC(dev->path.pci.devfn) == 0 ||

src/southbridge/intel/ibexpeak/nvs.h

@@ -137,7 +137,7 @@ typedef struct global_nvs_t {
 	u8	pavp; /* 0xe9 - IGD PAVP data */
 	u8	rsvd12; /* 0xea - rsvd */
 	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native pcie support */
+	u8	npce; /* 0xec - native PCIe support */
 	u8	plfl; /* 0xed - platform flavor */
 	u8	brev; /* 0xee - board revision */
 	u8	dpbm; /* 0xef - digital port b mode */

src/southbridge/intel/lynxpoint/acpi/globalnvs.asl

@@ -161,7 +161,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PAVP,	 8,	// 0xe9 - IGD PAVP data
 	Offset (0xeb),
 	OSCC,	 8,	// 0xeb - PCIe OSC control
-	NPCE,	 8,	// 0xec - native pcie support
+	NPCE,	 8,	// 0xec - native PCIe support
 	PLFL,	 8,	// 0xed - platform flavor
 	BREV,	 8,	// 0xee - board revision
 	DPBM,	 8,	// 0xef - digital port b mode

src/southbridge/intel/lynxpoint/nvs.h

@@ -114,7 +114,7 @@ typedef struct global_nvs_t {
 	u8	pavp; /* 0xe9 - IGD PAVP data */
 	u8	rsvd12; /* 0xea - rsvd */
 	u8	oscc; /* 0xeb - PCIe OSC control */
-	u8	npce; /* 0xec - native pcie support */
+	u8	npce; /* 0xec - native PCIe support */
 	u8	plfl; /* 0xed - platform flavor */
 	u8	brev; /* 0xee - board revision */
 	u8	dpbm; /* 0xef - digital port b mode */