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southbridge/intel: add IS_ENABLED() around Kconfig symbol references

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Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Martin Roth
2017-06-24 21:29:38 -06:00
parent 9fa8ebe1a4
commit 7a1a3ad2ce
48 changed files with 119 additions and 119 deletions
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4
src/southbridge/intel/ibexpeak/lpc.c
View File

@@ -71,7 +71,7 @@ static void pch_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
#if !CONFIG_SERIRQ_CONTINUOUS_MODE
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@@ -280,7 +280,7 @@ static void pch_rtc_init(struct device *dev)
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}

8
src/southbridge/intel/ibexpeak/me.c
View File

@@ -41,7 +41,7 @@
#include "me.h"
#include "pch.h"
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = {
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -470,7 +470,7 @@ static me_bios_path intel_me_path(device_t dev)
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -559,7 +559,7 @@ static int intel_me_extend_valid(device_t dev)
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif

2
src/southbridge/intel/ibexpeak/pch.h
View File

@@ -70,7 +70,7 @@ int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void gpi_route_interrupt(u8 gpi, u8 mode);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
#else /* __PRE_RAM__ */

2
src/southbridge/intel/ibexpeak/smi.c
View File

@@ -228,7 +228,7 @@ void southbridge_smm_init(void)
u16 pm1_en;
u32 gpe0_en;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif

8
src/southbridge/intel/ibexpeak/smihandler.c
View File

@@ -433,7 +433,7 @@ static void southbridge_smi_sleep(void)
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -535,7 +535,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -607,7 +607,7 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@@ -631,7 +631,7 @@ static void southbridge_smi_pm1(void)
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);