From 7a43532db8dafec341a635f9595ab9a1c1342401 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Thu, 9 Feb 2023 11:25:20 -0700 Subject: [PATCH] oryp11: Set dq_pins_interleaved Change-Id: I094e86b39df9cedcb2813a88785ef907b9bf2308 Signed-off-by: Tim Crawford --- src/mainboard/system76/rpl/variants/oryp11/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/system76/rpl/variants/oryp11/romstage.c b/src/mainboard/system76/rpl/variants/oryp11/romstage.c index 9b56345463..55807a65f7 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/romstage.c +++ b/src/mainboard/system76/rpl/variants/oryp11/romstage.c @@ -11,6 +11,9 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) .type = MEM_TYPE_DDR5, .ect = true, .LpDdrDqDqsReTraining = 1, + .ddr_config = { + .dq_pins_interleaved = true, + }, }; const struct mem_spd spd_info = { .topo = MEM_TOPO_DIMM_MODULE,