Add src/cpu/amd/model_gx2/cache_as_ram.inc missing from r5669
Part of converting GX2 to use CAR. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Joseph Smith <joe@settoplinux.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
Peter Stuge
parent
e474070bdd
commit
7a4952a54f
207
src/cpu/amd/model_gx2/cache_as_ram.inc
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207
src/cpu/amd/model_gx2/cache_as_ram.inc
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2010 Nils Jacobs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define GX2_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
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#define GX2_STACK_END GX2_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
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#define GX2_NUM_CACHELINES 0x080 /* there are 128lines per way */
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#define GX2_CACHELINE_SIZE 0x020 /* there are 32bytes per line */
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#define GX2_CACHEWAY_SIZE (GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE)
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#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
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#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
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#include <cpu/amd/gx2def.h>
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/***************************************************************************
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/**
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/** DCacheSetup
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/**
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/** Setup data cache for use as RAM for a stack.
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/**
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/** Max. size data cache =0x4000 (16KB)
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/**
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/***************************************************************************/
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DCacheSetup:
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/* Save the BIST result */
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movl %eax, %ebx
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invd
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/* set cache properties */
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movl $CPU_RCONF_DEFAULT, %ecx
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rdmsr
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movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */
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wrmsr
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/* in GX2 DCDIS is set after POR which disables the cache..., clear this bit */
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movl $CPU_DM_CONFIG0, %ecx
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rdmsr
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andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */
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wrmsr
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/* Get cleaned up. */
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xorl %edi, %edi
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xorl %esi, %esi
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xorl %ebp, %ebp
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/* DCache Ways0 through Ways3 will be tagged for GX2_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
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/* remember, there is NO stack yet... */
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/* Tell cache we want to fill WAY 0 starting at the top */
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xorl %edx, %edx
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xorl %eax, %eax
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movl $CPU_DC_INDEX, %ecx
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wrmsr
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/* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */
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movl $GX2_STACK_BASE, %ebp /* init to start address */
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orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */
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/* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */
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movl $GX2_NUM_CACHELINES, %edi
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DCacheSetupFillWay:
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/* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */
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/* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */
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movw $0x04, %si
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xorl %edx, %edx
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xorl %eax, %eax
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movl $CPU_DC_DATA, %ecx
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DCacheSetup_quadWordLoop:
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wrmsr
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decw %si
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jnz DCacheSetup_quadWordLoop
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/* Set the tag for this line,need to do this for every new cache line to validate it! */
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/* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */
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xorl %edx, %edx
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movl %ebp, %eax
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movl $CPU_DC_TAG, %ecx
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wrmsr
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/* switch to next line */
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/* lines are in Bits8:2 */
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/* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */
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movl $CPU_DC_INDEX, %ecx
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rdmsr
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addl $0x04, %eax /* inc DC_LINE. TODO: prob. would be more elegant to calc. this from counter var edi... */
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wrmsr
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decl %edi
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jnz DCacheSetupFillWay
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/* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */
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addl $GX2_CACHEWAY_SIZE, %ebp
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cmpl $GX2_STACK_END, %ebp
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jge leave_DCacheSetup
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movl $GX2_NUM_CACHELINES, %edi
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/* switch to next way */
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movl $CPU_DC_INDEX, %ecx
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rdmsr
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addl $0x01, %eax
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andl $0xFFFFFE03, %eax /* lets be sure: reset line index Bits8:2 */
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wrmsr
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jmp DCacheSetupFillWay
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leave_DCacheSetup:
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xorl %edi, %edi
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xorl %esi, %esi
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xorl %ebp, %ebp
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/* Disable the cache, but ... DO NOT INVALIDATE the tags. */
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/* Memory reads and writes will all hit in the cache. */
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/* Cache updates and memory write-backs will not occur ! */
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movl %cr0, %eax
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orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */
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movl %eax, %cr0
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/* Now point sp to the cached stack. */
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/* The stack will be fully functional at this location. No system memory is required at all ! */
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/* set up the stack pointer */
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movl $GX2_STACK_END, %eax
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movl %eax, %esp
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/* test the stack*/
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movl $0x0F0F05A5A, %edx
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pushl %edx
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popl %ecx
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cmpl %ecx, %edx
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je DCacheSetupGood
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post_code(0xc5)
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DCacheSetupBad:
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hlt /* issues */
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jmp DCacheSetupBad
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DCacheSetupGood:
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/* Go do early init and memory setup */
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/* Restore the BIST result */
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movl %ebx, %eax
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movl %esp, %ebp
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pushl %eax
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post_code(0x23)
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/* Call romstage.c main function */
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call main
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done_cache_as_ram_main:
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/* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
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push %edi
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mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
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push %esi
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mov $(CONFIG_DCACHE_RAM_BASE),%edi
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mov %edi,%esi
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cld
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rep movsl %ds:(%esi),%es:(%edi)
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pop %esi
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pop %edi
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/* Clear the cache out to ram */
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wbinvd
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/* re-enable the cache */
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movl %cr0, %eax
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xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */
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movl %eax, %cr0
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/* clear boot_complete flag */
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xorl %ebp, %ebp
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__main:
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post_code(0x11) /* post 11 */
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/* TODO For suspend/resume the cache will have to live between
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* CONFIG_RAMBASE and CONFIG_RAMTOP
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*/
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cld /* clear direction flag */
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/* copy coreboot from it's initial load location to
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* the location it is compiled to run at.
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* Normally this is copying from FLASH ROM to RAM.
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*/
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movl %ebp, %esi
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pushl %esi
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call copy_and_run
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.Lhlt:
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post_code(0xee) /* post fail ee */
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hlt
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jmp .Lhlt
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