sb/amd/rs690: Get rid of device_t
Use of device_t has been abandoned in ramstage. Change-Id: I818f808e1cd8b156158251724352f8be6041030c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Elyes HAOUAS
committed by
Kyösti Mälkki
Kyösti Mälkki
parent
d5c4aa7a0a
commit
7a4d41aa2d
@@ -26,13 +26,14 @@
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#include <delay.h>
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#include "rs690.h"
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static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
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static u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)
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{
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pci_write_config32(dev, index_reg, index);
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return pci_read_config32(dev, index_reg + 0x4);
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}
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static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
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static void nb_write_index(struct device *dev, u32 index_reg, u32 index,
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u32 data)
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{
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pci_write_config32(dev, index_reg, index);
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@@ -41,7 +42,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
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}
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/* extension registers */
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u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
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u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg)
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{
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/* get BAR3 base address for nbcfg0x1c */
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u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
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@@ -52,7 +53,8 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
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return *((u32 *) addr);
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}
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void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
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void pci_ext_write_config32(struct device *nb_dev, struct device *dev,
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u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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@@ -71,57 +73,58 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
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}
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}
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u32 nbmisc_read_index(device_t nb_dev, u32 index)
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u32 nbmisc_read_index(struct device *nb_dev, u32 index)
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{
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return nb_read_index((nb_dev), NBMISC_INDEX, (index));
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}
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void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
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void nbmisc_write_index(struct device *nb_dev, u32 index, u32 data)
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{
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nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
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}
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u32 nbpcie_p_read_index(device_t dev, u32 index)
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u32 nbpcie_p_read_index(struct device *dev, u32 index)
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{
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return nb_read_index((dev), NBPCIE_INDEX, (index));
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}
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void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
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void nbpcie_p_write_index(struct device *dev, u32 index, u32 data)
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{
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nb_write_index((dev), NBPCIE_INDEX, (index), (data));
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}
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u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
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u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index)
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{
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return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
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}
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void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
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void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data)
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{
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nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
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}
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u32 htiu_read_index(device_t nb_dev, u32 index)
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u32 htiu_read_index(struct device *nb_dev, u32 index)
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{
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return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
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}
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void htiu_write_index(device_t nb_dev, u32 index, u32 data)
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void htiu_write_index(struct device *nb_dev, u32 index, u32 data)
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{
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nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
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}
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u32 nbmc_read_index(device_t nb_dev, u32 index)
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u32 nbmc_read_index(struct device *nb_dev, u32 index)
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{
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return nb_read_index((nb_dev), NBMC_INDEX, (index));
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}
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void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
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void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)
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{
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nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
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}
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void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask,
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u32 val)
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{
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u32 reg_old, reg;
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reg = reg_old = pci_read_config32(nb_dev, reg_pos);
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@@ -132,7 +135,8 @@ void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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}
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}
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void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
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void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, u8 mask,
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u8 val)
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{
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u8 reg_old, reg;
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reg = reg_old = pci_read_config8(nb_dev, reg_pos);
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@@ -143,7 +147,7 @@ void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
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}
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}
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void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
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@@ -154,7 +158,7 @@ void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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}
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}
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void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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reg = reg_old = htiu_read_index(nb_dev, reg_pos);
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@@ -165,7 +169,8 @@ void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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}
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}
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void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask,
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u32 val)
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{
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u32 reg_old, reg;
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reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
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@@ -176,7 +181,7 @@ void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
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}
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}
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void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
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void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val)
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{
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u32 reg_old, reg;
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reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
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@@ -196,8 +201,8 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
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void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
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{
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/* K8 Function1 is address map */
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device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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if (in_out) {
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u32 dword, sblk;
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@@ -223,7 +228,8 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
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}
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}
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void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
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void PcieReleasePortTraining(struct device *nb_dev, struct device *dev,
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u32 port)
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{
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switch (port) {
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case 2: /* GFX, bit4-5 */
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@@ -246,7 +252,7 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
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* 0: no device is present.
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* 1: device is present and is trained.
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*/
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u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port)
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{
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u16 count = 5000;
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u32 lc_state, reg;
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@@ -305,7 +311,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
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* Compliant with CIM_33's ATINB_SetToms.
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* Set Top Of Memory below and above 4G.
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*/
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void rs690_set_tom(device_t nb_dev)
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void rs690_set_tom(struct device *nb_dev)
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{
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/* set TOM */
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#if IS_ENABLED(CONFIG_GFXUMA)
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@@ -31,7 +31,7 @@
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#define CLK_CNTL_DATA 0xC
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#ifdef UNUSED_CODE
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static u32 clkind_read(device_t dev, u32 index)
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static u32 clkind_read(struct device *dev, u32 index)
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{
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u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
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@@ -40,7 +40,7 @@ static u32 clkind_read(device_t dev, u32 index)
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}
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#endif
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static void clkind_write(device_t dev, u32 index, u32 data)
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static void clkind_write(struct device *dev, u32 index, u32 data)
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{
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u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
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/* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */
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@@ -53,7 +53,7 @@ static void clkind_write(device_t dev, u32 index, u32 data)
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* pci_dev_read_resources thinks it is a IO type.
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* We have to force it to mem type.
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*/
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static void rs690_gfx_read_resources(device_t dev)
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static void rs690_gfx_read_resources(struct device *dev)
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{
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printk(BIOS_INFO, "rs690_gfx_read_resources.\n");
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@@ -106,12 +106,12 @@ static void internal_gfx_pci_dev_init(struct device *dev)
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* Set registers in RS690 and CPU to enable the internal GFX.
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* Please refer to CIM source code and BKDG.
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*/
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static void rs690_internal_gfx_enable(device_t dev)
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static void rs690_internal_gfx_enable(struct device *dev)
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{
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u32 l_dword;
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int i;
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device_t k8_f2 = 0;
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device_t nb_dev = dev_find_slot(0, 0);
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struct device *k8_f2 = NULL;
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struct device *nb_dev = dev_find_slot(0, 0);
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printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
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nb_dev);
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@@ -182,7 +182,8 @@ static void rs690_internal_gfx_enable(device_t dev)
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/* TODO: the optimization of voltage and frequency */
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}
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static void gfx_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
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static void gfx_dev_set_subsystem(struct device *dev, unsigned vendor,
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unsigned device)
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{
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pci_write_config32(dev, 0x4c, ((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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@@ -218,7 +219,7 @@ static const struct pci_driver pcie_driver_690 __pci_driver = {
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};
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/* step 12 ~ step 14 from rpr */
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static void single_port_configuration(device_t nb_dev, device_t dev)
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static void single_port_configuration(struct device *nb_dev, struct device *dev)
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{
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u8 result, width;
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u32 reg32;
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@@ -276,7 +277,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
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}
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/* step 15 ~ step 18 from rpr */
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static void dual_port_configuration(device_t nb_dev, device_t dev)
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static void dual_port_configuration(struct device *nb_dev, struct device *dev)
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{
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u8 result, width;
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u32 reg32;
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@@ -355,10 +356,11 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
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* 101 = x12 (not supported)
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* 110 = x16
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*/
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static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
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static void dynamic_link_width_control(struct device *nb_dev,
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struct device *dev, u8 width)
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{
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u32 reg32;
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device_t sb_dev;
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struct device *sb_dev;
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struct southbridge_amd_rs690_config *cfg =
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(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
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@@ -401,7 +403,7 @@ static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
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/*
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* GFX Core initialization, dev2, dev3
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*/
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void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
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void rs690_gfx_init(struct device *nb_dev, struct device *dev, u32 port)
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{
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u16 reg16;
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struct southbridge_amd_rs690_config *cfg =
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@@ -22,11 +22,11 @@
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#include <arch/acpi.h>
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#include "rs690.h"
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static void ht_dev_set_resources(device_t dev)
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static void ht_dev_set_resources(struct device *dev)
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{
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#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
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unsigned reg;
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device_t k8_f1;
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struct device *k8_f1;
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resource_t rbase, rend;
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u32 base, limit;
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struct resource *resource;
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@@ -59,7 +59,8 @@ static void ht_dev_set_resources(device_t dev)
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}
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if ( !(base & 3) ) {
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u32 sblk;
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device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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struct device *k8_f0 =
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dev_find_slot(0, PCI_DEVFN(0x18, 0));
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/* Remember this resource has been stored. */
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resource->flags |= IORESOURCE_STORED;
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report_resource_stored(dev, resource, " <mmconfig>");
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@@ -87,7 +88,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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struct resource *res;
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resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default
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device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));
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struct device *dev = dev_find_slot(0,PCI_DEVFN(0,0));
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// we report mmconf base
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res = probe_resource(dev, 0x1C);
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if ( res )
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@@ -98,7 +99,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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return current;
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}
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static void ht_dev_read_resources(device_t dev)
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static void ht_dev_read_resources(struct device *dev)
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{
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#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
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struct resource *res;
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@@ -125,9 +126,9 @@ static void ht_dev_read_resources(device_t dev)
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}
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/* for UMA internal graphics */
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void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)
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void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev)
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{
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device_t k8_f0;
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struct device *k8_f0;
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u8 reg;
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k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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@@ -170,7 +171,8 @@ static void pcie_init(struct device *dev)
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pci_write_config32(dev, 0x4C, dword);
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}
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static void ht_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
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static void ht_dev_set_subsystem(struct device *dev, unsigned vendor,
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unsigned device)
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{
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pci_write_config32(dev, 0x50, ((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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@@ -44,10 +44,11 @@ PCIE_CFG AtiPcieCfg = {
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0 /* GppPwr */
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};
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static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port);
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static void ValidatePortEn(device_t nb_dev);
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static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev,
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u32 port);
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static void ValidatePortEn(struct device *nb_dev);
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static void ValidatePortEn(device_t nb_dev)
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static void ValidatePortEn(struct device *nb_dev)
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{
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}
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@@ -56,7 +57,8 @@ static void ValidatePortEn(device_t nb_dev)
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* Compliant with CIM_33's PCIEPowerOffGppPorts
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* Power off unused GPP lines
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*****************************************************************/
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static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
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static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev,
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u32 port)
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{
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u32 reg;
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u16 state_save;
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@@ -119,7 +121,8 @@ static void pcie_init(struct device *dev)
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/**********************************************************************
|
||||
**********************************************************************/
|
||||
static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
|
||||
static void switching_gpp_configurations(struct device *nb_dev,
|
||||
struct device *sb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
struct southbridge_amd_rs690_config *cfg =
|
||||
@@ -164,7 +167,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
|
||||
* The rs690 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
|
||||
* Space to a 256MB range within the first 4GB of addressable memory.
|
||||
*****************************************************************/
|
||||
void enable_pcie_bar3(device_t nb_dev)
|
||||
void enable_pcie_bar3(struct device *nb_dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
|
||||
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
|
||||
@@ -180,7 +183,7 @@ void enable_pcie_bar3(device_t nb_dev)
|
||||
* We should disable bar3 when we want to exit rs690_enable, because bar3 will be
|
||||
* remapped in set_resource later.
|
||||
*****************************************************************/
|
||||
void disable_pcie_bar3(device_t nb_dev)
|
||||
void disable_pcie_bar3(struct device *nb_dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
|
||||
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */
|
||||
@@ -197,11 +200,11 @@ void disable_pcie_bar3(device_t nb_dev)
|
||||
* port:
|
||||
* p2p bridge number, 4-8
|
||||
*****************************************/
|
||||
void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
|
||||
void rs690_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port)
|
||||
{
|
||||
u8 reg8;
|
||||
u16 reg16;
|
||||
device_t sb_dev;
|
||||
struct device *sb_dev;
|
||||
struct southbridge_amd_rs690_config *cfg =
|
||||
(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
|
||||
printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
|
||||
@@ -334,7 +337,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
|
||||
/*****************************************
|
||||
* Compliant with CIM_33's PCIEConfigureGPPCore
|
||||
*****************************************/
|
||||
void config_gpp_core(device_t nb_dev, device_t sb_dev)
|
||||
void config_gpp_core(struct device *nb_dev, struct device *sb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
struct southbridge_amd_rs690_config *cfg =
|
||||
@@ -357,7 +360,7 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
|
||||
/*****************************************
|
||||
* Compliant with CIM_33's PCIEMiscClkProg
|
||||
*****************************************/
|
||||
void pcie_config_misc_clk(device_t nb_dev)
|
||||
void pcie_config_misc_clk(struct device *nb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
struct bus pbus; /* fake bus for dev0 fun1 */
|
||||
|
||||
@@ -29,7 +29,7 @@
|
||||
/*****************************************
|
||||
* Compliant with CIM_33's ATINB_MiscClockCtrl
|
||||
*****************************************/
|
||||
void static rs690_config_misc_clk(device_t nb_dev)
|
||||
void static rs690_config_misc_clk(struct device *nb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
u16 word;
|
||||
@@ -100,7 +100,7 @@ void static rs690_config_misc_clk(device_t nb_dev)
|
||||
set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
|
||||
}
|
||||
|
||||
static u32 get_vid_did(device_t dev)
|
||||
static u32 get_vid_did(struct device *dev)
|
||||
{
|
||||
return pci_read_config32(dev, 0);
|
||||
}
|
||||
@@ -119,9 +119,9 @@ static u32 get_vid_did(device_t dev)
|
||||
* case 0 will be called twice, one is by CPU in hypertransport.c line458,
|
||||
* the other is by rs690.
|
||||
***********************************************/
|
||||
void rs690_enable(device_t dev)
|
||||
void rs690_enable(struct device *dev)
|
||||
{
|
||||
device_t nb_dev = 0, sb_dev = 0;
|
||||
struct device *nb_dev = NULL, *sb_dev = NULL;
|
||||
int dev_ind;
|
||||
|
||||
printk(BIOS_INFO, "rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
|
||||
|
||||
@@ -101,37 +101,44 @@ typedef enum _NB_REVISION_ {
|
||||
extern PCIE_CFG AtiPcieCfg;
|
||||
|
||||
/* ----------------- export functions ----------------- */
|
||||
u32 nbmisc_read_index(device_t nb_dev, u32 index);
|
||||
void nbmisc_write_index(device_t nb_dev, u32 index, u32 data);
|
||||
u32 nbpcie_p_read_index(device_t dev, u32 index);
|
||||
void nbpcie_p_write_index(device_t dev, u32 index, u32 data);
|
||||
u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);
|
||||
void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);
|
||||
u32 htiu_read_index(device_t nb_dev, u32 index);
|
||||
void htiu_write_index(device_t nb_dev, u32 index, u32 data);
|
||||
u32 nbmc_read_index(device_t nb_dev, u32 index);
|
||||
void nbmc_write_index(device_t nb_dev, u32 index, u32 data);
|
||||
u32 nbmisc_read_index(struct device *nb_dev, u32 index);
|
||||
void nbmisc_write_index(struct device *nb_dev, u32 index, u32 data);
|
||||
u32 nbpcie_p_read_index(struct device *dev, u32 index);
|
||||
void nbpcie_p_write_index(struct device *dev, u32 index, u32 data);
|
||||
u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index);
|
||||
void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data);
|
||||
u32 htiu_read_index(struct device *nb_dev, u32 index);
|
||||
void htiu_write_index(struct device *nb_dev, u32 index, u32 data);
|
||||
u32 nbmc_read_index(struct device *nb_dev, u32 index);
|
||||
void nbmc_write_index(struct device *nb_dev, u32 index, u32 data);
|
||||
|
||||
u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);
|
||||
void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);
|
||||
u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg);
|
||||
void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg,
|
||||
u32 mask, u32 val);
|
||||
|
||||
void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val);
|
||||
void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void rs690_set_tom(device_t nb_dev);
|
||||
void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask,
|
||||
u32 val);
|
||||
void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, u8 mask,
|
||||
u8 val);
|
||||
void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask,
|
||||
u32 val);
|
||||
void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask,
|
||||
u32 val);
|
||||
void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask,
|
||||
u32 val);
|
||||
void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void rs690_set_tom(struct device *nb_dev);
|
||||
|
||||
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
|
||||
void enable_pcie_bar3(device_t nb_dev);
|
||||
void disable_pcie_bar3(device_t nb_dev);
|
||||
void enable_pcie_bar3(struct device *nb_dev);
|
||||
void disable_pcie_bar3(struct device *nb_dev);
|
||||
|
||||
void rs690_enable(device_t dev);
|
||||
void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
|
||||
void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port);
|
||||
void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);
|
||||
void config_gpp_core(device_t nb_dev, device_t sb_dev);
|
||||
void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
|
||||
u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
|
||||
void rs690_enable(struct device *dev);
|
||||
void rs690_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port);
|
||||
void rs690_gfx_init(struct device *nb_dev, struct device *dev, u32 port);
|
||||
void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev);
|
||||
void config_gpp_core(struct device *nb_dev, struct device *sb_dev);
|
||||
void PcieReleasePortTraining(struct device *nb_dev, struct device *dev,
|
||||
u32 port);
|
||||
u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port);
|
||||
#endif /* __RS690_H__ */
|
||||
|
||||
Reference in New Issue
Block a user