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- Modify the freebios tree so the pci config space api is mostly in sync between

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code that runs without ram and code that runs with ram.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
2003-06-12 19:23:51 +00:00
parent 540ae01cd3
commit 7a5416af95
9 changed files with 174 additions and 226 deletions
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12
src/southbridge/amd/amd8111/amd8111_ide.c
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@@ -14,7 +14,7 @@ static void ide_init(struct device *dev)
printk_debug("ide_init\n");
pci_read_config_word(dev, 0x40, &word);
word = pci_read_config16(dev, 0x40);
/* Ensure prefetch is disabled */
word &= ~((1 << 15) | (1 << 13));
if (enable_b) {
@@ -31,10 +31,10 @@ static void ide_init(struct device *dev)
word |= (1<<12);
word |= (1<<14);
pci_write_config_word(dev, 0x40, word);
pci_write_config16(dev, 0x40, word);
word = 0x0f;
pci_write_config_word(dev, 0x42, word);
pci_write_config16(dev, 0x42, word);
/* The AMD768 has a bug where the BM DMA address must be
* 256 byte aligned while it is only 16 bytes long.
@@ -43,11 +43,11 @@ static void ide_init(struct device *dev)
* FIXME: I assume the 8111 does the same thing. We should
* clarify. stepan@suse.de
*/
pci_write_config_dword(dev, 0x20, 0xf01);
pci_write_config32(dev, 0x20, 0xf01);
pci_write_config_dword(dev, 0x48, 0x205e5e5e);
pci_write_config32(dev, 0x48, 0x205e5e5e);
word = 0x06a;
pci_write_config_word(dev, 0x4c, word);
pci_write_config16(dev, 0x4c, word);
}
static struct device_operations ide_ops = {

15
src/southbridge/amd/amd8111/amd8111_lpc.c
View File

@@ -1,3 +1,6 @@
/*
* (C) 2003 Linux Networx
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -94,24 +97,24 @@ static void lpc_init(struct device *dev)
#if 0
/* IO APIC initialization */
pci_read_config_byte(dev, 0x4B, &byte);
byte = pci_read_config8(dev, 0x4B);
byte |= 1;
pci_write_config_byte(dev, 0x4B, byte);
pci_write_config8(dev, 0x4B, byte);
setup_ioapic();
#endif
/* posted memory write enable */
pci_read_config_byte(dev, 0x46, &byte);
pci_write_config_byte(dev, 0x46, byte | (1<<0));
byte = pci_read_config8(dev, 0x46);
pci_write_config8(dev, 0x46, byte | (1<<0));
/* power after power fail */
pci_read_config_byte(dev, 0x43, &byte);
byte = pci_read_config8(dev, 0x43);
if (pwr_on) {
byte &= ~(1<<6);
} else {
byte |= (1<<6);
}
pci_write_config_byte(dev, 0x43, byte);
pci_write_config8(dev, 0x43, byte);
}

4
src/southbridge/amd/amd8111/amd8111_usb.c
View File

@@ -9,8 +9,8 @@ static void usb_init(struct device *dev)
uint32_t cmd;
printk_debug("USB: Setting up controller.. ");
pci_read_config_dword(dev, PCI_COMMAND, &cmd);
pci_write_config_dword(dev, PCI_COMMAND,
cmd = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);